237 lines
6.4 KiB
C
237 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef UFS_QCOM_H_
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#define UFS_QCOM_H_
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#include <linux/reset-controller.h>
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#include <linux/reset.h>
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#include <soc/qcom/ice.h>
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#include <ufs/ufshcd.h>
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#define MPHY_TX_FSM_STATE 0x41
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#define TX_FSM_HIBERN8 0x1
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#define HBRN8_POLL_TOUT_MS 100
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#define DEFAULT_CLK_RATE_HZ 1000000
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#define MAX_SUPP_MAC 64
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#define MAX_ESI_VEC 32
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#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)
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#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)
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#define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
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#define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4)
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#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
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/* QCOM UFS host controller vendor specific registers */
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enum {
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REG_UFS_SYS1CLK_1US = 0xC0,
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REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
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REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
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REG_UFS_PA_ERR_CODE = 0xCC,
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/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
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REG_UFS_PARAM0 = 0xD0,
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/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
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REG_UFS_CFG0 = 0xD8,
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REG_UFS_CFG1 = 0xDC,
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REG_UFS_CFG2 = 0xE0,
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REG_UFS_HW_VERSION = 0xE4,
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UFS_TEST_BUS = 0xE8,
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UFS_TEST_BUS_CTRL_0 = 0xEC,
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UFS_TEST_BUS_CTRL_1 = 0xF0,
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UFS_TEST_BUS_CTRL_2 = 0xF4,
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UFS_UNIPRO_CFG = 0xF8,
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/*
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* QCOM UFS host controller vendor specific registers
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* added in HW Version 3.0.0
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*/
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UFS_AH8_CFG = 0xFC,
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REG_UFS_CFG3 = 0x271C,
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REG_UFS_DEBUG_SPARE_CFG = 0x284C,
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};
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/* QCOM UFS host controller vendor specific debug registers */
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enum {
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UFS_DBG_RD_REG_UAWM = 0x100,
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UFS_DBG_RD_REG_UARM = 0x200,
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UFS_DBG_RD_REG_TXUC = 0x300,
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UFS_DBG_RD_REG_RXUC = 0x400,
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UFS_DBG_RD_REG_DFC = 0x500,
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UFS_DBG_RD_REG_TRLUT = 0x600,
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UFS_DBG_RD_REG_TMRLUT = 0x700,
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UFS_UFS_DBG_RD_REG_OCSC = 0x800,
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UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
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UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
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UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
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UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
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};
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enum {
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UFS_MEM_CQIS_VS = 0x8,
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};
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#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
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#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
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/* bit definitions for REG_UFS_CFG0 register */
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#define QUNIPRO_G4_SEL BIT(5)
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/* bit definitions for REG_UFS_CFG1 register */
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#define QUNIPRO_SEL BIT(0)
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#define UFS_PHY_SOFT_RESET BIT(1)
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#define UTP_DBG_RAMS_EN BIT(17)
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#define TEST_BUS_EN BIT(18)
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#define TEST_BUS_SEL GENMASK(22, 19)
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#define UFS_REG_TEST_BUS_EN BIT(30)
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/* bit definitions for REG_UFS_CFG2 register */
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#define UAWM_HW_CGC_EN BIT(0)
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#define UARM_HW_CGC_EN BIT(1)
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#define TXUC_HW_CGC_EN BIT(2)
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#define RXUC_HW_CGC_EN BIT(3)
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#define DFC_HW_CGC_EN BIT(4)
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#define TRLUT_HW_CGC_EN BIT(5)
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#define TMRLUT_HW_CGC_EN BIT(6)
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#define OCSC_HW_CGC_EN BIT(7)
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/* bit definitions for REG_UFS_CFG3 register */
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#define ESI_VEC_MASK GENMASK(22, 12)
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/* bit definitions for REG_UFS_PARAM0 */
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#define MAX_HS_GEAR_MASK GENMASK(6, 4)
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#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x))
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/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
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#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
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#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
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TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
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DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
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TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
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/* QUniPro Vendor specific attributes */
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#define PA_VS_CONFIG_REG1 0x9000
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#define DME_VS_CORE_CLK_CTRL 0xD002
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/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
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#define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16)
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#define CLK_1US_CYCLES_MASK GENMASK(7, 0)
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#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
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#define PA_VS_CORE_CLK_40NS_CYCLES 0x9007
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#define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0)
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/* QCOM UFS host controller core clk frequencies */
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#define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38
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#define UNIPRO_CORE_CLK_FREQ_75_MHZ 75
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#define UNIPRO_CORE_CLK_FREQ_100_MHZ 100
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#define UNIPRO_CORE_CLK_FREQ_150_MHZ 150
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#define UNIPRO_CORE_CLK_FREQ_300_MHZ 300
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#define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202
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#define UNIPRO_CORE_CLK_FREQ_403_MHZ 403
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static inline void
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ufs_qcom_get_controller_revision(struct ufs_hba *hba,
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u8 *major, u16 *minor, u16 *step)
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{
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u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
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*major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
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*minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
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*step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
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};
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static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
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{
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ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
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/*
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* Make sure assertion of ufs phy reset is written to
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* register before returning
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*/
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mb();
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}
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static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
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{
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ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);
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/*
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* Make sure de-assertion of ufs phy reset is written to
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* register before returning
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*/
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mb();
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}
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/* Host controller hardware version: major.minor.step */
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struct ufs_hw_version {
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u16 step;
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u16 minor;
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u8 major;
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};
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struct ufs_qcom_testbus {
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u8 select_major;
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u8 select_minor;
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};
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struct gpio_desc;
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struct ufs_qcom_host {
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struct phy *generic_phy;
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struct ufs_hba *hba;
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struct ufs_pa_layer_attr dev_req_params;
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struct clk_bulk_data *clks;
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u32 num_clks;
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bool is_lane_clks_enabled;
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struct icc_path *icc_ddr;
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struct icc_path *icc_cpu;
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#ifdef CONFIG_SCSI_UFS_CRYPTO
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struct qcom_ice *ice;
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#endif
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void __iomem *dev_ref_clk_ctrl_mmio;
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bool is_dev_ref_clk_enabled;
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struct ufs_hw_version hw_ver;
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u32 dev_ref_clk_en_mask;
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struct ufs_qcom_testbus testbus;
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/* Reset control of HCI */
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struct reset_control *core_reset;
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struct reset_controller_dev rcdev;
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struct gpio_desc *device_reset;
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struct ufs_host_params host_params;
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u32 phy_gear;
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bool esi_enabled;
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};
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static inline u32
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ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
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{
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if (host->hw_ver.major <= 0x02)
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return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
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return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
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};
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#define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
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#define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
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#define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
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#define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1))
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int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
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#endif /* UFS_QCOM_H_ */
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