1397 lines
41 KiB
C
1397 lines
41 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
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* (host mode only)
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*
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* Copyright (C) 2009 - 2015 Xilinx, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/spi/spi-mem.h>
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/* Generic QSPI register offsets */
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#define GQSPI_CONFIG_OFST 0x00000100
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#define GQSPI_ISR_OFST 0x00000104
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#define GQSPI_IDR_OFST 0x0000010C
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#define GQSPI_IER_OFST 0x00000108
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#define GQSPI_IMASK_OFST 0x00000110
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#define GQSPI_EN_OFST 0x00000114
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#define GQSPI_TXD_OFST 0x0000011C
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#define GQSPI_RXD_OFST 0x00000120
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#define GQSPI_TX_THRESHOLD_OFST 0x00000128
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#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
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#define IOU_TAPDLY_BYPASS_OFST 0x0000003C
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#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
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#define GQSPI_GEN_FIFO_OFST 0x00000140
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#define GQSPI_SEL_OFST 0x00000144
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#define GQSPI_GF_THRESHOLD_OFST 0x00000150
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#define GQSPI_FIFO_CTRL_OFST 0x0000014C
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#define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
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#define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
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#define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
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#define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
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#define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
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#define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
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#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
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#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
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#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
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#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
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/* GQSPI register bit masks */
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#define GQSPI_SEL_MASK 0x00000001
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#define GQSPI_EN_MASK 0x00000001
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#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
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#define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
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#define GQSPI_IDR_ALL_MASK 0x00000FBE
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#define GQSPI_CFG_MODE_EN_MASK 0xC0000000
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#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
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#define GQSPI_CFG_ENDIAN_MASK 0x04000000
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#define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
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#define GQSPI_CFG_WP_HOLD_MASK 0x00080000
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#define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
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#define GQSPI_CFG_CLK_PHA_MASK 0x00000004
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#define GQSPI_CFG_CLK_POL_MASK 0x00000002
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#define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
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#define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
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#define GQSPI_GENFIFO_DATA_XFER 0x00000100
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#define GQSPI_GENFIFO_EXP 0x00000200
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#define GQSPI_GENFIFO_MODE_SPI 0x00000400
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#define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
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#define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
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#define GQSPI_GENFIFO_MODE_MASK 0x00000C00
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#define GQSPI_GENFIFO_CS_LOWER 0x00001000
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#define GQSPI_GENFIFO_CS_UPPER 0x00002000
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#define GQSPI_GENFIFO_BUS_LOWER 0x00004000
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#define GQSPI_GENFIFO_BUS_UPPER 0x00008000
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#define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
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#define GQSPI_GENFIFO_BUS_MASK 0x0000C000
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#define GQSPI_GENFIFO_TX 0x00010000
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#define GQSPI_GENFIFO_RX 0x00020000
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#define GQSPI_GENFIFO_STRIPE 0x00040000
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#define GQSPI_GENFIFO_POLL 0x00080000
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#define GQSPI_GENFIFO_EXP_START 0x00000100
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#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
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#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
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#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
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#define GQSPI_ISR_RXEMPTY_MASK 0x00000800
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#define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
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#define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
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#define GQSPI_ISR_TXEMPTY_MASK 0x00000100
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#define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
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#define GQSPI_ISR_RXFULL_MASK 0x00000020
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#define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
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#define GQSPI_ISR_TXFULL_MASK 0x00000008
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#define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
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#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
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#define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
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#define GQSPI_IER_RXEMPTY_MASK 0x00000800
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#define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
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#define GQSPI_IER_RXNEMPTY_MASK 0x00000010
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#define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
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#define GQSPI_IER_TXEMPTY_MASK 0x00000100
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#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
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#define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
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#define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
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#define GQSPI_ISR_IDR_MASK 0x00000994
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#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
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#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
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#define GQSPI_IRQ_MASK 0x00000980
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#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
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#define GQSPI_GENFIFO_CS_SETUP 0x4
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#define GQSPI_GENFIFO_CS_HOLD 0x3
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#define GQSPI_TXD_DEPTH 64
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#define GQSPI_RX_FIFO_THRESHOLD 32
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#define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
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#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
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#define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
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GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
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#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
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#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
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#define GQSPI_SELECT_FLASH_CS_LOWER 0x1
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#define GQSPI_SELECT_FLASH_CS_UPPER 0x2
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#define GQSPI_SELECT_FLASH_CS_BOTH 0x3
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#define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
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#define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
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#define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
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#define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
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#define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
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#define GQSPI_SELECT_MODE_SPI 0x1
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#define GQSPI_SELECT_MODE_DUALSPI 0x2
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#define GQSPI_SELECT_MODE_QUADSPI 0x4
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#define GQSPI_DMA_UNALIGN 0x3
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#define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
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#define GQSPI_MAX_NUM_CS 2 /* Maximum number of chip selects */
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#define GQSPI_USE_DATA_DLY 0x1
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#define GQSPI_USE_DATA_DLY_SHIFT 31
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#define GQSPI_DATA_DLY_ADJ_VALUE 0x2
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#define GQSPI_DATA_DLY_ADJ_SHIFT 28
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#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1
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#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 0x3
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#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
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#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 0x2
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/* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
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#define QSPI_QUIRK_HAS_TAPDELAY BIT(0)
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#define GQSPI_FREQ_37_5MHZ 37500000
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#define GQSPI_FREQ_40MHZ 40000000
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#define GQSPI_FREQ_100MHZ 100000000
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#define GQSPI_FREQ_150MHZ 150000000
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#define SPI_AUTOSUSPEND_TIMEOUT 3000
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enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
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/**
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* struct qspi_platform_data - zynqmp qspi platform data structure
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* @quirks: Flags is used to identify the platform
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*/
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struct qspi_platform_data {
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u32 quirks;
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};
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/**
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* struct zynqmp_qspi - Defines qspi driver instance
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* @ctlr: Pointer to the spi controller information
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* @regs: Virtual address of the QSPI controller registers
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* @refclk: Pointer to the peripheral clock
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* @pclk: Pointer to the APB clock
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* @irq: IRQ number
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* @dev: Pointer to struct device
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* @txbuf: Pointer to the TX buffer
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* @rxbuf: Pointer to the RX buffer
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* @bytes_to_transfer: Number of bytes left to transfer
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* @bytes_to_receive: Number of bytes left to receive
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* @genfifocs: Used for chip select
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* @genfifobus: Used to select the upper or lower bus
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* @dma_rx_bytes: Remaining bytes to receive by DMA mode
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* @dma_addr: DMA address after mapping the kernel buffer
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* @genfifoentry: Used for storing the genfifoentry instruction.
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* @mode: Defines the mode in which QSPI is operating
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* @data_completion: completion structure
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* @op_lock: Operational lock
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* @speed_hz: Current SPI bus clock speed in hz
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* @has_tapdelay: Used for tapdelay register available in qspi
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*/
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struct zynqmp_qspi {
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struct spi_controller *ctlr;
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void __iomem *regs;
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struct clk *refclk;
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struct clk *pclk;
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int irq;
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struct device *dev;
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const void *txbuf;
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void *rxbuf;
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int bytes_to_transfer;
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int bytes_to_receive;
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u32 genfifocs;
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u32 genfifobus;
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u32 dma_rx_bytes;
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dma_addr_t dma_addr;
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u32 genfifoentry;
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enum mode_type mode;
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struct completion data_completion;
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struct mutex op_lock;
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u32 speed_hz;
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bool has_tapdelay;
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};
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/**
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* zynqmp_gqspi_read - For GQSPI controller read operation
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* @xqspi: Pointer to the zynqmp_qspi structure
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* @offset: Offset from where to read
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* Return: Value at the offset
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*/
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static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
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{
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return readl_relaxed(xqspi->regs + offset);
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}
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/**
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* zynqmp_gqspi_write - For GQSPI controller write operation
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* @xqspi: Pointer to the zynqmp_qspi structure
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* @offset: Offset where to write
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* @val: Value to be written
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*/
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static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
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u32 val)
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{
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writel_relaxed(val, (xqspi->regs + offset));
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}
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/**
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* zynqmp_gqspi_selecttarget - For selection of target device
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* @instanceptr: Pointer to the zynqmp_qspi structure
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* @targetcs: For chip select
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* @targetbus: To check which bus is selected- upper or lower
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*/
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static void zynqmp_gqspi_selecttarget(struct zynqmp_qspi *instanceptr,
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u8 targetcs, u8 targetbus)
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{
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/*
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* Bus and CS lines selected here will be updated in the instance and
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* used for subsequent GENFIFO entries during transfer.
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*/
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/* Choose target select line */
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switch (targetcs) {
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case GQSPI_SELECT_FLASH_CS_BOTH:
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instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
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GQSPI_GENFIFO_CS_UPPER;
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break;
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case GQSPI_SELECT_FLASH_CS_UPPER:
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instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
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break;
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case GQSPI_SELECT_FLASH_CS_LOWER:
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instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
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break;
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default:
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dev_warn(instanceptr->dev, "Invalid target select\n");
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}
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/* Choose the bus */
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switch (targetbus) {
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case GQSPI_SELECT_FLASH_BUS_BOTH:
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instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
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GQSPI_GENFIFO_BUS_UPPER;
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break;
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case GQSPI_SELECT_FLASH_BUS_UPPER:
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instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
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break;
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case GQSPI_SELECT_FLASH_BUS_LOWER:
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instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
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break;
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default:
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dev_warn(instanceptr->dev, "Invalid target bus\n");
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}
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}
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/**
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* zynqmp_qspi_set_tapdelay: To configure qspi tap delays
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* @xqspi: Pointer to the zynqmp_qspi structure
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* @baudrateval: Buadrate to configure
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*/
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static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
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{
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u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
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u32 reqhz = 0;
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clk_rate = clk_get_rate(xqspi->refclk);
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reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
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if (!xqspi->has_tapdelay) {
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if (reqhz <= GQSPI_FREQ_40MHZ) {
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zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
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PM_TAPDELAY_BYPASS_ENABLE);
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} else if (reqhz <= GQSPI_FREQ_100MHZ) {
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zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
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PM_TAPDELAY_BYPASS_ENABLE);
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lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
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datadlyadj |= ((GQSPI_USE_DATA_DLY <<
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GQSPI_USE_DATA_DLY_SHIFT)
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| (GQSPI_DATA_DLY_ADJ_VALUE <<
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GQSPI_DATA_DLY_ADJ_SHIFT));
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} else if (reqhz <= GQSPI_FREQ_150MHZ) {
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lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK;
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}
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} else {
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if (reqhz <= GQSPI_FREQ_37_5MHZ) {
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tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
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TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
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} else if (reqhz <= GQSPI_FREQ_100MHZ) {
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tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
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TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
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lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
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datadlyadj |= (GQSPI_USE_DATA_DLY <<
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GQSPI_USE_DATA_DLY_SHIFT);
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} else if (reqhz <= GQSPI_FREQ_150MHZ) {
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lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK
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| (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
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GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT));
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}
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zynqmp_gqspi_write(xqspi,
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IOU_TAPDLY_BYPASS_OFST, tapdlybypass);
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}
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zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
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zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
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}
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/**
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* zynqmp_qspi_init_hw - Initialize the hardware
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* @xqspi: Pointer to the zynqmp_qspi structure
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*
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* The default settings of the QSPI controller's configurable parameters on
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* reset are
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* - Host mode
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* - TX threshold set to 1
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* - RX threshold set to 1
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* - Flash memory interface mode enabled
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* This function performs the following actions
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* - Disable and clear all the interrupts
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* - Enable manual target select
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* - Enable manual start
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* - Deselect all the chip select lines
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* - Set the little endian mode of TX FIFO
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* - Set clock phase
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* - Set clock polarity and
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* - Enable the QSPI controller
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*/
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static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
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{
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u32 config_reg, baud_rate_val = 0;
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ulong clk_rate;
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/* Select the GQSPI mode */
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zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
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/* Clear and disable interrupts */
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zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
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zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
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GQSPI_ISR_WR_TO_CLR_MASK);
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/* Clear the DMA STS */
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zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
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zynqmp_gqspi_read(xqspi,
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GQSPI_QSPIDMA_DST_I_STS_OFST));
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zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
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zynqmp_gqspi_read(xqspi,
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GQSPI_QSPIDMA_DST_STS_OFST) |
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GQSPI_QSPIDMA_DST_STS_WTC);
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zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
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zynqmp_gqspi_write(xqspi,
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GQSPI_QSPIDMA_DST_I_DIS_OFST,
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GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
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/* Disable the GQSPI */
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zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
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config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
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config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
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/* Manual start */
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config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
|
|
/* Little endian by default */
|
|
config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
|
|
/* Disable poll time out */
|
|
config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
|
|
/* Set hold bit */
|
|
config_reg |= GQSPI_CFG_WP_HOLD_MASK;
|
|
/* Clear pre-scalar by default */
|
|
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
|
|
/* Set CPHA */
|
|
if (xqspi->ctlr->mode_bits & SPI_CPHA)
|
|
config_reg |= GQSPI_CFG_CLK_PHA_MASK;
|
|
else
|
|
config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
|
|
/* Set CPOL */
|
|
if (xqspi->ctlr->mode_bits & SPI_CPOL)
|
|
config_reg |= GQSPI_CFG_CLK_POL_MASK;
|
|
else
|
|
config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
|
|
|
|
/* Set the clock frequency */
|
|
clk_rate = clk_get_rate(xqspi->refclk);
|
|
while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
|
|
(clk_rate /
|
|
(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)
|
|
baud_rate_val++;
|
|
|
|
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
|
|
config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
|
|
|
|
/* Set the tapdelay for clock frequency */
|
|
zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
|
|
|
|
/* Clear the TX and RX FIFO */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
|
|
GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
|
|
GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
|
|
GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
|
|
/* Reset thresholds */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
|
|
GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
|
|
GQSPI_RX_FIFO_THRESHOLD);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
|
|
GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
|
|
zynqmp_gqspi_selecttarget(xqspi,
|
|
GQSPI_SELECT_FLASH_CS_LOWER,
|
|
GQSPI_SELECT_FLASH_BUS_LOWER);
|
|
/* Initialize DMA */
|
|
zynqmp_gqspi_write(xqspi,
|
|
GQSPI_QSPIDMA_DST_CTRL_OFST,
|
|
GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
|
|
|
|
/* Enable the GQSPI */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_copy_read_data - Copy data to RX buffer
|
|
* @xqspi: Pointer to the zynqmp_qspi structure
|
|
* @data: The variable where data is stored
|
|
* @size: Number of bytes to be copied from data to RX buffer
|
|
*/
|
|
static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
|
|
ulong data, u8 size)
|
|
{
|
|
memcpy(xqspi->rxbuf, &data, size);
|
|
xqspi->rxbuf += size;
|
|
xqspi->bytes_to_receive -= size;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_chipselect - Select or deselect the chip select line
|
|
* @qspi: Pointer to the spi_device structure
|
|
* @is_high: Select(0) or deselect (1) the chip select line
|
|
*/
|
|
static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
|
|
{
|
|
struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller);
|
|
ulong timeout;
|
|
u32 genfifoentry = 0, statusreg;
|
|
|
|
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
|
|
|
|
if (!is_high) {
|
|
if (!spi_get_chipselect(qspi, 0)) {
|
|
xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
|
|
xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
|
|
} else {
|
|
xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
|
|
xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
|
|
}
|
|
genfifoentry |= xqspi->genfifobus;
|
|
genfifoentry |= xqspi->genfifocs;
|
|
genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
|
|
} else {
|
|
genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
|
|
}
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
|
|
|
|
/* Manually start the generic FIFO command */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK);
|
|
|
|
timeout = jiffies + msecs_to_jiffies(1000);
|
|
|
|
/* Wait until the generic FIFO command is empty */
|
|
do {
|
|
statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
|
|
|
|
if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
|
|
(statusreg & GQSPI_ISR_TXEMPTY_MASK))
|
|
break;
|
|
cpu_relax();
|
|
} while (!time_after_eq(jiffies, timeout));
|
|
|
|
if (time_after_eq(jiffies, timeout))
|
|
dev_err(xqspi->dev, "Chip select timed out\n");
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
|
|
* @xqspi: xqspi is a pointer to the GQSPI instance
|
|
* @spimode: spimode - SPI or DUAL or QUAD.
|
|
* Return: Mask to set desired SPI mode in GENFIFO entry.
|
|
*/
|
|
static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
|
|
u8 spimode)
|
|
{
|
|
u32 mask = 0;
|
|
|
|
switch (spimode) {
|
|
case GQSPI_SELECT_MODE_DUALSPI:
|
|
mask = GQSPI_GENFIFO_MODE_DUALSPI;
|
|
break;
|
|
case GQSPI_SELECT_MODE_QUADSPI:
|
|
mask = GQSPI_GENFIFO_MODE_QUADSPI;
|
|
break;
|
|
case GQSPI_SELECT_MODE_SPI:
|
|
mask = GQSPI_GENFIFO_MODE_SPI;
|
|
break;
|
|
default:
|
|
dev_warn(xqspi->dev, "Invalid SPI mode\n");
|
|
}
|
|
|
|
return mask;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_config_op - Configure QSPI controller for specified
|
|
* transfer
|
|
* @xqspi: Pointer to the zynqmp_qspi structure
|
|
* @qspi: Pointer to the spi_device structure
|
|
*
|
|
* Sets the operational mode of QSPI controller for the next QSPI transfer and
|
|
* sets the requested clock frequency.
|
|
*
|
|
* Return: Always 0
|
|
*
|
|
* Note:
|
|
* If the requested frequency is not an exact match with what can be
|
|
* obtained using the pre-scalar value, the driver sets the clock
|
|
* frequency which is lower than the requested frequency (maximum lower)
|
|
* for the transfer.
|
|
*
|
|
* If the requested frequency is higher or lower than that is supported
|
|
* by the QSPI controller the driver will set the highest or lowest
|
|
* frequency supported by controller.
|
|
*/
|
|
static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
|
|
struct spi_device *qspi)
|
|
{
|
|
ulong clk_rate;
|
|
u32 config_reg, req_speed_hz, baud_rate_val = 0;
|
|
|
|
req_speed_hz = qspi->max_speed_hz;
|
|
|
|
if (xqspi->speed_hz != req_speed_hz) {
|
|
xqspi->speed_hz = req_speed_hz;
|
|
|
|
/* Set the clock frequency */
|
|
/* If req_speed_hz == 0, default to lowest speed */
|
|
clk_rate = clk_get_rate(xqspi->refclk);
|
|
|
|
while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
|
|
(clk_rate /
|
|
(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) >
|
|
req_speed_hz)
|
|
baud_rate_val++;
|
|
|
|
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
|
|
|
|
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
|
|
config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
|
|
zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_setup_op - Configure the QSPI controller
|
|
* @qspi: Pointer to the spi_device structure
|
|
*
|
|
* Sets the operational mode of QSPI controller for the next QSPI transfer,
|
|
* baud rate and divisor value to setup the requested qspi clock.
|
|
*
|
|
* Return: 0 on success; error value otherwise.
|
|
*/
|
|
static int zynqmp_qspi_setup_op(struct spi_device *qspi)
|
|
{
|
|
struct spi_controller *ctlr = qspi->controller;
|
|
struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
|
|
|
|
if (ctlr->busy)
|
|
return -EBUSY;
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
|
|
* the FIFO or the bytes required to be
|
|
* transmitted.
|
|
* @xqspi: Pointer to the zynqmp_qspi structure
|
|
* @size: Number of bytes to be copied from TX buffer to TX FIFO
|
|
*/
|
|
static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
|
|
{
|
|
u32 count = 0, intermediate;
|
|
|
|
while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
|
|
if (xqspi->bytes_to_transfer >= 4) {
|
|
memcpy(&intermediate, xqspi->txbuf, 4);
|
|
xqspi->txbuf += 4;
|
|
xqspi->bytes_to_transfer -= 4;
|
|
count += 4;
|
|
} else {
|
|
memcpy(&intermediate, xqspi->txbuf,
|
|
xqspi->bytes_to_transfer);
|
|
xqspi->txbuf += xqspi->bytes_to_transfer;
|
|
xqspi->bytes_to_transfer = 0;
|
|
count += xqspi->bytes_to_transfer;
|
|
}
|
|
zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
|
|
* the FIFO.
|
|
* @xqspi: Pointer to the zynqmp_qspi structure
|
|
* @size: Number of bytes to be copied from RX buffer to RX FIFO
|
|
*/
|
|
static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
|
|
{
|
|
ulong data;
|
|
int count = 0;
|
|
|
|
while ((count < size) && (xqspi->bytes_to_receive > 0)) {
|
|
if (xqspi->bytes_to_receive >= 4) {
|
|
(*(u32 *)xqspi->rxbuf) =
|
|
zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
|
|
xqspi->rxbuf += 4;
|
|
xqspi->bytes_to_receive -= 4;
|
|
count += 4;
|
|
} else {
|
|
data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
|
|
count += xqspi->bytes_to_receive;
|
|
zynqmp_qspi_copy_read_data(xqspi, data,
|
|
xqspi->bytes_to_receive);
|
|
xqspi->bytes_to_receive = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
|
|
* @xqspi: Pointer to the zynqmp_qspi structure
|
|
* @nbits: Transfer/Receive buswidth.
|
|
* @genfifoentry: Variable in which GENFIFO mask is saved
|
|
*/
|
|
static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
|
|
u32 genfifoentry)
|
|
{
|
|
u32 transfer_len = 0;
|
|
|
|
if (xqspi->txbuf) {
|
|
genfifoentry &= ~GQSPI_GENFIFO_RX;
|
|
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
|
|
genfifoentry |= GQSPI_GENFIFO_TX;
|
|
transfer_len = xqspi->bytes_to_transfer;
|
|
} else if (xqspi->rxbuf) {
|
|
genfifoentry &= ~GQSPI_GENFIFO_TX;
|
|
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
|
|
genfifoentry |= GQSPI_GENFIFO_RX;
|
|
if (xqspi->mode == GQSPI_MODE_DMA)
|
|
transfer_len = xqspi->dma_rx_bytes;
|
|
else
|
|
transfer_len = xqspi->bytes_to_receive;
|
|
} else {
|
|
/* Sending dummy circles here */
|
|
genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
|
|
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
|
|
transfer_len = xqspi->bytes_to_transfer;
|
|
}
|
|
genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
|
|
xqspi->genfifoentry = genfifoentry;
|
|
|
|
if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
|
|
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
|
|
genfifoentry |= transfer_len;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
|
|
} else {
|
|
int tempcount = transfer_len;
|
|
u32 exponent = 8; /* 2^8 = 256 */
|
|
u8 imm_data = tempcount & 0xFF;
|
|
|
|
tempcount &= ~(tempcount & 0xFF);
|
|
/* Immediate entry */
|
|
if (tempcount != 0) {
|
|
/* Exponent entries */
|
|
genfifoentry |= GQSPI_GENFIFO_EXP;
|
|
while (tempcount != 0) {
|
|
if (tempcount & GQSPI_GENFIFO_EXP_START) {
|
|
genfifoentry &=
|
|
~GQSPI_GENFIFO_IMM_DATA_MASK;
|
|
genfifoentry |= exponent;
|
|
zynqmp_gqspi_write(xqspi,
|
|
GQSPI_GEN_FIFO_OFST,
|
|
genfifoentry);
|
|
}
|
|
tempcount = tempcount >> 1;
|
|
exponent++;
|
|
}
|
|
}
|
|
if (imm_data != 0) {
|
|
genfifoentry &= ~GQSPI_GENFIFO_EXP;
|
|
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
|
|
genfifoentry |= (u8)(imm_data & 0xFF);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
|
|
genfifoentry);
|
|
}
|
|
}
|
|
if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
|
|
/* Dummy generic FIFO entry */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
|
|
* controller
|
|
* @xqspi: zynqmp_qspi instance pointer
|
|
*
|
|
* This function handles DMA interrupt only.
|
|
*/
|
|
static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
|
|
{
|
|
u32 config_reg, genfifoentry;
|
|
|
|
dma_unmap_single(xqspi->dev, xqspi->dma_addr,
|
|
xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
|
|
xqspi->rxbuf += xqspi->dma_rx_bytes;
|
|
xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
|
|
xqspi->dma_rx_bytes = 0;
|
|
|
|
/* Disabling the DMA interrupts */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
|
|
GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
|
|
|
|
if (xqspi->bytes_to_receive > 0) {
|
|
/* Switch to IO mode,for remaining bytes to receive */
|
|
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
|
|
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
|
|
|
|
/* Initiate the transfer of remaining bytes */
|
|
genfifoentry = xqspi->genfifoentry;
|
|
genfifoentry |= xqspi->bytes_to_receive;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
|
|
|
|
/* Dummy generic FIFO entry */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
|
|
|
|
/* Manual start */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
(zynqmp_gqspi_read(xqspi,
|
|
GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK));
|
|
|
|
/* Enable the RX interrupts for IO mode */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
|
GQSPI_IER_GENFIFOEMPTY_MASK |
|
|
GQSPI_IER_RXNEMPTY_MASK |
|
|
GQSPI_IER_RXEMPTY_MASK);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
|
|
* @irq: IRQ number
|
|
* @dev_id: Pointer to the xqspi structure
|
|
*
|
|
* This function handles TX empty only.
|
|
* On TX empty interrupt this function reads the received data from RX FIFO
|
|
* and fills the TX FIFO if there is any data remaining to be transferred.
|
|
*
|
|
* Return: IRQ_HANDLED when interrupt is handled
|
|
* IRQ_NONE otherwise.
|
|
*/
|
|
static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
|
|
{
|
|
struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u32 status, mask, dma_status = 0;
|
|
|
|
status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
|
|
mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
|
|
|
|
/* Read and clear DMA status */
|
|
if (xqspi->mode == GQSPI_MODE_DMA) {
|
|
dma_status =
|
|
zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
|
|
dma_status);
|
|
}
|
|
|
|
if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
|
|
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
|
|
zynqmp_process_dma_irq(xqspi);
|
|
ret = IRQ_HANDLED;
|
|
} else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
|
|
(mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
|
|
zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
|
|
((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
|
|
zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
|
|
complete(&xqspi->data_completion);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
|
|
* @xqspi: xqspi is a pointer to the GQSPI instance.
|
|
*
|
|
* Return: 0 on success; error value otherwise.
|
|
*/
|
|
static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
|
|
{
|
|
u32 rx_bytes, rx_rem, config_reg;
|
|
dma_addr_t addr;
|
|
u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
|
|
|
|
if (xqspi->bytes_to_receive < 8 ||
|
|
((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
|
|
/* Setting to IO mode */
|
|
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
|
|
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
|
|
xqspi->mode = GQSPI_MODE_IO;
|
|
xqspi->dma_rx_bytes = 0;
|
|
return 0;
|
|
}
|
|
|
|
rx_rem = xqspi->bytes_to_receive % 4;
|
|
rx_bytes = (xqspi->bytes_to_receive - rx_rem);
|
|
|
|
addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
|
|
rx_bytes, DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(xqspi->dev, addr)) {
|
|
dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
xqspi->dma_rx_bytes = rx_bytes;
|
|
xqspi->dma_addr = addr;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
|
|
(u32)(addr & 0xffffffff));
|
|
addr = ((addr >> 16) >> 16);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
|
|
((u32)addr) & 0xfff);
|
|
|
|
/* Enabling the DMA mode */
|
|
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
|
|
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
|
|
config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
|
|
|
|
/* Switch to DMA mode */
|
|
xqspi->mode = GQSPI_MODE_DMA;
|
|
|
|
/* Write the number of bytes to transfer */
|
|
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
|
|
* TX FIFO, and fills the TX FIFO with as many
|
|
* bytes as possible.
|
|
* @xqspi: Pointer to the GQSPI instance.
|
|
* @tx_nbits: Transfer buswidth.
|
|
* @genfifoentry: Variable in which GENFIFO mask is returned
|
|
* to calling function
|
|
*/
|
|
static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
|
|
u32 genfifoentry)
|
|
{
|
|
u32 config_reg;
|
|
|
|
zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
|
|
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
|
|
if (xqspi->mode == GQSPI_MODE_DMA) {
|
|
config_reg = zynqmp_gqspi_read(xqspi,
|
|
GQSPI_CONFIG_OFST);
|
|
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
config_reg);
|
|
xqspi->mode = GQSPI_MODE_IO;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
|
|
* RX DMA operation.
|
|
* @xqspi: xqspi is a pointer to the GQSPI instance.
|
|
* @rx_nbits: Receive buswidth.
|
|
* @genfifoentry: genfifoentry is pointer to the variable in which
|
|
* GENFIFO mask is returned to calling function
|
|
*
|
|
* Return: 0 on success; error value otherwise.
|
|
*/
|
|
static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
|
|
u32 genfifoentry)
|
|
{
|
|
int ret;
|
|
|
|
ret = zynqmp_qspi_setuprxdma(xqspi);
|
|
if (ret)
|
|
return ret;
|
|
zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_suspend - Suspend method for the QSPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function stops the QSPI driver queue and disables the QSPI controller
|
|
*
|
|
* Return: Always 0
|
|
*/
|
|
static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
|
|
{
|
|
struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
|
|
struct spi_controller *ctlr = xqspi->ctlr;
|
|
int ret;
|
|
|
|
ret = spi_controller_suspend(ctlr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_resume - Resume method for the QSPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* The function starts the QSPI driver queue and initializes the QSPI
|
|
* controller
|
|
*
|
|
* Return: 0 on success; error value otherwise
|
|
*/
|
|
static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
|
|
{
|
|
struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
|
|
struct spi_controller *ctlr = xqspi->ctlr;
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
|
|
|
|
spi_controller_resume(ctlr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function disables the clocks
|
|
*
|
|
* Return: Always 0
|
|
*/
|
|
static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
|
|
{
|
|
struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(xqspi->refclk);
|
|
clk_disable_unprepare(xqspi->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_runtime_resume - Runtime resume method for the SPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function enables the clocks
|
|
*
|
|
* Return: 0 on success and error value on error
|
|
*/
|
|
static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
|
|
{
|
|
struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(xqspi->pclk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable APB clock.\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(xqspi->refclk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable device clock.\n");
|
|
clk_disable_unprepare(xqspi->pclk);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_exec_op() - Initiates the QSPI transfer
|
|
* @mem: The SPI memory
|
|
* @op: The memory operation to execute
|
|
*
|
|
* Executes a memory operation.
|
|
*
|
|
* This function first selects the chip and starts the memory operation.
|
|
*
|
|
* Return: 0 in case of success, a negative error code otherwise.
|
|
*/
|
|
static int zynqmp_qspi_exec_op(struct spi_mem *mem,
|
|
const struct spi_mem_op *op)
|
|
{
|
|
struct zynqmp_qspi *xqspi = spi_controller_get_devdata
|
|
(mem->spi->controller);
|
|
int err = 0, i;
|
|
u32 genfifoentry = 0;
|
|
u16 opcode = op->cmd.opcode;
|
|
u64 opaddr;
|
|
|
|
dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
|
|
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
|
|
op->dummy.buswidth, op->data.buswidth);
|
|
|
|
mutex_lock(&xqspi->op_lock);
|
|
zynqmp_qspi_config_op(xqspi, mem->spi);
|
|
zynqmp_qspi_chipselect(mem->spi, false);
|
|
genfifoentry |= xqspi->genfifocs;
|
|
genfifoentry |= xqspi->genfifobus;
|
|
|
|
if (op->cmd.opcode) {
|
|
reinit_completion(&xqspi->data_completion);
|
|
xqspi->txbuf = &opcode;
|
|
xqspi->rxbuf = NULL;
|
|
xqspi->bytes_to_transfer = op->cmd.nbytes;
|
|
xqspi->bytes_to_receive = 0;
|
|
zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
|
GQSPI_IER_GENFIFOEMPTY_MASK |
|
|
GQSPI_IER_TXNOT_FULL_MASK);
|
|
if (!wait_for_completion_timeout
|
|
(&xqspi->data_completion, msecs_to_jiffies(1000))) {
|
|
err = -ETIMEDOUT;
|
|
goto return_err;
|
|
}
|
|
}
|
|
|
|
if (op->addr.nbytes) {
|
|
xqspi->txbuf = &opaddr;
|
|
for (i = 0; i < op->addr.nbytes; i++) {
|
|
*(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
|
|
(8 * (op->addr.nbytes - i - 1));
|
|
}
|
|
|
|
reinit_completion(&xqspi->data_completion);
|
|
xqspi->rxbuf = NULL;
|
|
xqspi->bytes_to_transfer = op->addr.nbytes;
|
|
xqspi->bytes_to_receive = 0;
|
|
zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
zynqmp_gqspi_read(xqspi,
|
|
GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
|
GQSPI_IER_TXEMPTY_MASK |
|
|
GQSPI_IER_GENFIFOEMPTY_MASK |
|
|
GQSPI_IER_TXNOT_FULL_MASK);
|
|
if (!wait_for_completion_timeout
|
|
(&xqspi->data_completion, msecs_to_jiffies(1000))) {
|
|
err = -ETIMEDOUT;
|
|
goto return_err;
|
|
}
|
|
}
|
|
|
|
if (op->dummy.nbytes) {
|
|
xqspi->txbuf = NULL;
|
|
xqspi->rxbuf = NULL;
|
|
/*
|
|
* xqspi->bytes_to_transfer here represents the dummy circles
|
|
* which need to be sent.
|
|
*/
|
|
xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
|
|
xqspi->bytes_to_receive = 0;
|
|
/*
|
|
* Using op->data.buswidth instead of op->dummy.buswidth here because
|
|
* we need to use it to configure the correct SPI mode.
|
|
*/
|
|
zynqmp_qspi_write_op(xqspi, op->data.buswidth,
|
|
genfifoentry);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK);
|
|
}
|
|
|
|
if (op->data.nbytes) {
|
|
reinit_completion(&xqspi->data_completion);
|
|
if (op->data.dir == SPI_MEM_DATA_OUT) {
|
|
xqspi->txbuf = (u8 *)op->data.buf.out;
|
|
xqspi->rxbuf = NULL;
|
|
xqspi->bytes_to_transfer = op->data.nbytes;
|
|
xqspi->bytes_to_receive = 0;
|
|
zynqmp_qspi_write_op(xqspi, op->data.buswidth,
|
|
genfifoentry);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
zynqmp_gqspi_read
|
|
(xqspi, GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK);
|
|
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
|
GQSPI_IER_TXEMPTY_MASK |
|
|
GQSPI_IER_GENFIFOEMPTY_MASK |
|
|
GQSPI_IER_TXNOT_FULL_MASK);
|
|
} else {
|
|
xqspi->txbuf = NULL;
|
|
xqspi->rxbuf = (u8 *)op->data.buf.in;
|
|
xqspi->bytes_to_receive = op->data.nbytes;
|
|
xqspi->bytes_to_transfer = 0;
|
|
err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
|
|
genfifoentry);
|
|
if (err)
|
|
goto return_err;
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
|
zynqmp_gqspi_read
|
|
(xqspi, GQSPI_CONFIG_OFST) |
|
|
GQSPI_CFG_START_GEN_FIFO_MASK);
|
|
if (xqspi->mode == GQSPI_MODE_DMA) {
|
|
zynqmp_gqspi_write
|
|
(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
|
|
GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
|
|
} else {
|
|
zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
|
|
GQSPI_IER_GENFIFOEMPTY_MASK |
|
|
GQSPI_IER_RXNEMPTY_MASK |
|
|
GQSPI_IER_RXEMPTY_MASK);
|
|
}
|
|
}
|
|
if (!wait_for_completion_timeout
|
|
(&xqspi->data_completion, msecs_to_jiffies(1000)))
|
|
err = -ETIMEDOUT;
|
|
}
|
|
|
|
return_err:
|
|
|
|
zynqmp_qspi_chipselect(mem->spi, true);
|
|
mutex_unlock(&xqspi->op_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
|
|
zynqmp_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
|
|
};
|
|
|
|
static const struct qspi_platform_data versal_qspi_def = {
|
|
.quirks = QSPI_QUIRK_HAS_TAPDELAY,
|
|
};
|
|
|
|
static const struct of_device_id zynqmp_qspi_of_match[] = {
|
|
{ .compatible = "xlnx,zynqmp-qspi-1.0"},
|
|
{ .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
|
|
{ /* End of table */ }
|
|
};
|
|
|
|
static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
|
|
.exec_op = zynqmp_qspi_exec_op,
|
|
};
|
|
|
|
/**
|
|
* zynqmp_qspi_probe - Probe method for the QSPI driver
|
|
* @pdev: Pointer to the platform_device structure
|
|
*
|
|
* This function initializes the driver data structures and the hardware.
|
|
*
|
|
* Return: 0 on success; error value otherwise
|
|
*/
|
|
static int zynqmp_qspi_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
struct spi_controller *ctlr;
|
|
struct zynqmp_qspi *xqspi;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
u32 num_cs;
|
|
const struct qspi_platform_data *p_data;
|
|
|
|
ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi));
|
|
if (!ctlr)
|
|
return -ENOMEM;
|
|
|
|
xqspi = spi_controller_get_devdata(ctlr);
|
|
xqspi->dev = dev;
|
|
xqspi->ctlr = ctlr;
|
|
platform_set_drvdata(pdev, xqspi);
|
|
|
|
p_data = of_device_get_match_data(&pdev->dev);
|
|
if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))
|
|
xqspi->has_tapdelay = true;
|
|
|
|
xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(xqspi->regs)) {
|
|
ret = PTR_ERR(xqspi->regs);
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(xqspi->pclk)) {
|
|
dev_err(dev, "pclk clock not found.\n");
|
|
ret = PTR_ERR(xqspi->pclk);
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
|
|
if (IS_ERR(xqspi->refclk)) {
|
|
dev_err(dev, "ref_clk clock not found.\n");
|
|
ret = PTR_ERR(xqspi->refclk);
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
ret = clk_prepare_enable(xqspi->pclk);
|
|
if (ret) {
|
|
dev_err(dev, "Unable to enable APB clock.\n");
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
ret = clk_prepare_enable(xqspi->refclk);
|
|
if (ret) {
|
|
dev_err(dev, "Unable to enable device clock.\n");
|
|
goto clk_dis_pclk;
|
|
}
|
|
|
|
init_completion(&xqspi->data_completion);
|
|
|
|
mutex_init(&xqspi->op_lock);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
|
|
goto clk_dis_all;
|
|
}
|
|
|
|
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
|
|
SPI_TX_DUAL | SPI_TX_QUAD;
|
|
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
|
|
xqspi->speed_hz = ctlr->max_speed_hz;
|
|
|
|
/* QSPI controller initializations */
|
|
zynqmp_qspi_init_hw(xqspi);
|
|
|
|
xqspi->irq = platform_get_irq(pdev, 0);
|
|
if (xqspi->irq < 0) {
|
|
ret = xqspi->irq;
|
|
goto clk_dis_all;
|
|
}
|
|
ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
|
|
0, pdev->name, xqspi);
|
|
if (ret != 0) {
|
|
ret = -ENXIO;
|
|
dev_err(dev, "request_irq failed\n");
|
|
goto clk_dis_all;
|
|
}
|
|
|
|
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
|
|
if (ret)
|
|
goto clk_dis_all;
|
|
|
|
ret = of_property_read_u32(np, "num-cs", &num_cs);
|
|
if (ret < 0) {
|
|
ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
|
|
} else if (num_cs > GQSPI_MAX_NUM_CS) {
|
|
ret = -EINVAL;
|
|
dev_err(&pdev->dev, "only %d chip selects are available\n",
|
|
GQSPI_MAX_NUM_CS);
|
|
goto clk_dis_all;
|
|
} else {
|
|
ctlr->num_chipselect = num_cs;
|
|
}
|
|
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
ctlr->mem_ops = &zynqmp_qspi_mem_ops;
|
|
ctlr->setup = zynqmp_qspi_setup_op;
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
ctlr->dev.of_node = np;
|
|
ctlr->auto_runtime_pm = true;
|
|
|
|
ret = devm_spi_register_controller(&pdev->dev, ctlr);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "spi_register_controller failed\n");
|
|
goto clk_dis_all;
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
clk_dis_all:
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
clk_disable_unprepare(xqspi->refclk);
|
|
clk_dis_pclk:
|
|
clk_disable_unprepare(xqspi->pclk);
|
|
remove_ctlr:
|
|
spi_controller_put(ctlr);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* zynqmp_qspi_remove - Remove method for the QSPI driver
|
|
* @pdev: Pointer to the platform_device structure
|
|
*
|
|
* This function is called if a device is physically removed from the system or
|
|
* if the driver module is being unloaded. It frees all resources allocated to
|
|
* the device.
|
|
*
|
|
* Return: 0 Always
|
|
*/
|
|
static void zynqmp_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
clk_disable_unprepare(xqspi->refclk);
|
|
clk_disable_unprepare(xqspi->pclk);
|
|
}
|
|
|
|
MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
|
|
|
|
static struct platform_driver zynqmp_qspi_driver = {
|
|
.probe = zynqmp_qspi_probe,
|
|
.remove_new = zynqmp_qspi_remove,
|
|
.driver = {
|
|
.name = "zynqmp-qspi",
|
|
.of_match_table = zynqmp_qspi_of_match,
|
|
.pm = &zynqmp_qspi_dev_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(zynqmp_qspi_driver);
|
|
|
|
MODULE_AUTHOR("Xilinx, Inc.");
|
|
MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
|
|
MODULE_LICENSE("GPL");
|