101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/drivers/pcmcia/soc_common.h
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*
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* Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
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*
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* This file contains definitions for the PCMCIA support code common to
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* integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
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*/
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#ifndef _ASM_ARCH_PCMCIA
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#define _ASM_ARCH_PCMCIA
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/* include the world */
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <pcmcia/cistpl.h>
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#include <pcmcia/soc_common.h>
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struct device;
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struct gpio_desc;
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struct pcmcia_low_level;
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struct regulator;
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struct skt_dev_info {
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int nskt;
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struct soc_pcmcia_socket skt[];
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};
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struct soc_pcmcia_timing {
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unsigned short io;
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unsigned short mem;
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unsigned short attr;
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};
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extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_pcmcia_timing *);
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void soc_pcmcia_init_one(struct soc_pcmcia_socket *skt,
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const struct pcmcia_low_level *ops, struct device *dev);
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void soc_pcmcia_remove_one(struct soc_pcmcia_socket *skt);
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int soc_pcmcia_add_one(struct soc_pcmcia_socket *skt);
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int soc_pcmcia_request_gpiods(struct soc_pcmcia_socket *skt);
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void soc_common_cf_socket_state(struct soc_pcmcia_socket *skt,
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struct pcmcia_state *state);
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int soc_pcmcia_regulator_set(struct soc_pcmcia_socket *skt,
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struct soc_pcmcia_regulator *r, int v);
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#ifdef CONFIG_PCMCIA_DEBUG
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extern void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func,
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int lvl, const char *fmt, ...);
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#define debug(skt, lvl, fmt, arg...) \
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soc_pcmcia_debug(skt, __func__, lvl, fmt , ## arg)
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#else
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#define debug(skt, lvl, fmt, arg...) do { } while (0)
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#endif
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/*
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* The PC Card Standard, Release 7, section 4.13.4, says that twIORD
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* has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
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* a minimum value of 165ns, as well. Section 4.7.2 (describing
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* common and attribute memory write timing) says that twWE has a
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* minimum value of 150ns for a 250ns cycle time (for 5V operation;
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* see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
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* operation, also section 4.7.4). Section 4.7.3 says that taOE
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* has a maximum value of 150ns for a 300ns cycle time (for 5V
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* operation), or 300ns for a 600ns cycle time (for 3.3V operation).
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*
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* When configuring memory maps, Card Services appears to adopt the policy
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* that a memory access time of "0" means "use the default." The default
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* PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
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* and memory command width time is 150ns; the PCMCIA 3.3V attribute and
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* memory command width time is 300ns.
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*/
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#define SOC_PCMCIA_IO_ACCESS (165)
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#define SOC_PCMCIA_5V_MEM_ACCESS (150)
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#define SOC_PCMCIA_3V_MEM_ACCESS (300)
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#define SOC_PCMCIA_ATTR_MEM_ACCESS (300)
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/*
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* The socket driver actually works nicely in interrupt-driven form,
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* so the (relatively infrequent) polling is "just to be sure."
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*/
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#define SOC_PCMCIA_POLL_PERIOD (2*HZ)
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/* I/O pins replacing memory pins
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* (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
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*
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* These signals change meaning when going from memory-only to
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* memory-or-I/O interface:
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*/
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#define iostschg bvd1
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#define iospkr bvd2
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#endif
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