235 lines
7.7 KiB
C
235 lines
7.7 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Core driver for the Ocelot chip family.
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*
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* The VSC7511, 7512, 7513, and 7514 can be controlled internally via an
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* on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is
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* intended to be the bus-agnostic glue between, for example, the SPI bus and
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* the child devices.
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*
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* Copyright 2021-2022 Innovative Advantage Inc.
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*
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* Author: Colin Foster <colin.foster@in-advantage.com>
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/ocelot.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <soc/mscc/ocelot.h>
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#include "ocelot.h"
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#define REG_GCB_SOFT_RST 0x0008
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#define BIT_SOFT_CHIP_RST BIT(0)
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#define VSC7512_MIIM0_RES_START 0x7107009c
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#define VSC7512_MIIM1_RES_START 0x710700c0
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#define VSC7512_MIIM_RES_SIZE 0x00000024
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#define VSC7512_PHY_RES_START 0x710700f0
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#define VSC7512_PHY_RES_SIZE 0x00000004
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#define VSC7512_GPIO_RES_START 0x71070034
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#define VSC7512_GPIO_RES_SIZE 0x0000006c
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#define VSC7512_SIO_CTRL_RES_START 0x710700f8
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#define VSC7512_SIO_CTRL_RES_SIZE 0x00000100
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#define VSC7512_HSIO_RES_START 0x710d0000
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#define VSC7512_HSIO_RES_SIZE 0x00000128
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#define VSC7512_ANA_RES_START 0x71880000
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#define VSC7512_ANA_RES_SIZE 0x00010000
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#define VSC7512_QS_RES_START 0x71080000
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#define VSC7512_QS_RES_SIZE 0x00000100
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#define VSC7512_QSYS_RES_START 0x71800000
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#define VSC7512_QSYS_RES_SIZE 0x00200000
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#define VSC7512_REW_RES_START 0x71030000
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#define VSC7512_REW_RES_SIZE 0x00010000
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#define VSC7512_SYS_RES_START 0x71010000
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#define VSC7512_SYS_RES_SIZE 0x00010000
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#define VSC7512_S0_RES_START 0x71040000
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#define VSC7512_S1_RES_START 0x71050000
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#define VSC7512_S2_RES_START 0x71060000
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#define VCAP_RES_SIZE 0x00000400
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#define VSC7512_PORT_0_RES_START 0x711e0000
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#define VSC7512_PORT_1_RES_START 0x711f0000
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#define VSC7512_PORT_2_RES_START 0x71200000
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#define VSC7512_PORT_3_RES_START 0x71210000
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#define VSC7512_PORT_4_RES_START 0x71220000
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#define VSC7512_PORT_5_RES_START 0x71230000
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#define VSC7512_PORT_6_RES_START 0x71240000
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#define VSC7512_PORT_7_RES_START 0x71250000
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#define VSC7512_PORT_8_RES_START 0x71260000
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#define VSC7512_PORT_9_RES_START 0x71270000
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#define VSC7512_PORT_10_RES_START 0x71280000
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#define VSC7512_PORT_RES_SIZE 0x00010000
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#define VSC7512_GCB_RST_SLEEP_US 100
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#define VSC7512_GCB_RST_TIMEOUT_US 100000
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static int ocelot_gcb_chip_rst_status(struct ocelot_ddata *ddata)
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{
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int val, err;
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err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val);
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if (err)
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return err;
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return val;
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}
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int ocelot_chip_reset(struct device *dev)
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{
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struct ocelot_ddata *ddata = dev_get_drvdata(dev);
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int ret, val;
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/*
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* Reset the entire chip here to put it into a completely known state.
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* Other drivers may want to reset their own subsystems. The register
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* self-clears, so one write is all that is needed and wait for it to
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* clear.
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*/
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ret = regmap_write(ddata->gcb_regmap, REG_GCB_SOFT_RST, BIT_SOFT_CHIP_RST);
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if (ret)
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return ret;
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return readx_poll_timeout(ocelot_gcb_chip_rst_status, ddata, val, !val,
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VSC7512_GCB_RST_SLEEP_US, VSC7512_GCB_RST_TIMEOUT_US);
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}
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EXPORT_SYMBOL_NS(ocelot_chip_reset, MFD_OCELOT);
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static const struct resource vsc7512_miim0_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim0"),
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DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE, "gcb_phy"),
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};
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static const struct resource vsc7512_miim1_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim1"),
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};
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static const struct resource vsc7512_pinctrl_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE, "gcb_gpio"),
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};
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static const struct resource vsc7512_sgpio_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"),
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};
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static const struct resource vsc7512_serdes_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"),
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};
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static const struct resource vsc7512_switch_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, "ana"),
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DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"),
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DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, "qs"),
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DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"),
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DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, "rew"),
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DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, "sys"),
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DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VCAP_RES_SIZE, "s0"),
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DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VCAP_RES_SIZE, "s1"),
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DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VCAP_RES_SIZE, "s2"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"),
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DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10")
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};
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static const struct mfd_cell vsc7512_devs[] = {
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{
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.name = "ocelot-pinctrl",
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.of_compatible = "mscc,ocelot-pinctrl",
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.num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources),
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.resources = vsc7512_pinctrl_resources,
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}, {
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.name = "ocelot-sgpio",
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.of_compatible = "mscc,ocelot-sgpio",
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.num_resources = ARRAY_SIZE(vsc7512_sgpio_resources),
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.resources = vsc7512_sgpio_resources,
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}, {
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.name = "ocelot-miim0",
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.of_compatible = "mscc,ocelot-miim",
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.of_reg = VSC7512_MIIM0_RES_START,
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.use_of_reg = true,
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.num_resources = ARRAY_SIZE(vsc7512_miim0_resources),
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.resources = vsc7512_miim0_resources,
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}, {
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.name = "ocelot-miim1",
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.of_compatible = "mscc,ocelot-miim",
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.of_reg = VSC7512_MIIM1_RES_START,
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.use_of_reg = true,
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.num_resources = ARRAY_SIZE(vsc7512_miim1_resources),
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.resources = vsc7512_miim1_resources,
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}, {
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.name = "ocelot-serdes",
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.of_compatible = "mscc,vsc7514-serdes",
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.num_resources = ARRAY_SIZE(vsc7512_serdes_resources),
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.resources = vsc7512_serdes_resources,
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}, {
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.name = "ocelot-ext-switch",
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.of_compatible = "mscc,vsc7512-switch",
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.num_resources = ARRAY_SIZE(vsc7512_switch_resources),
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.resources = vsc7512_switch_resources,
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},
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};
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static void ocelot_core_try_add_regmap(struct device *dev,
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const struct resource *res)
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{
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if (dev_get_regmap(dev, res->name))
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return;
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ocelot_spi_init_regmap(dev, res);
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}
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static void ocelot_core_try_add_regmaps(struct device *dev,
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const struct mfd_cell *cell)
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{
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int i;
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for (i = 0; i < cell->num_resources; i++)
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ocelot_core_try_add_regmap(dev, &cell->resources[i]);
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}
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int ocelot_core_init(struct device *dev)
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{
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int i, ndevs;
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ndevs = ARRAY_SIZE(vsc7512_devs);
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for (i = 0; i < ndevs; i++)
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ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]);
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL);
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}
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EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT);
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MODULE_DESCRIPTION("Externally Controlled Ocelot Chip Driver");
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MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
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MODULE_LICENSE("GPL");
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MODULE_IMPORT_NS(MFD_OCELOT_SPI);
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