257 lines
6.9 KiB
C
257 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Analog Devices Generic AXI ADC IP core
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* Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
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*
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* Copyright 2012-2020 Analog Devices Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/fpga/adi-axi-common.h>
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#include <linux/iio/backend.h>
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#include <linux/iio/buffer-dmaengine.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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/*
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* Register definitions:
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* https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
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*/
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/* ADC controls */
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#define ADI_AXI_REG_RSTN 0x0040
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#define ADI_AXI_REG_RSTN_CE_N BIT(2)
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#define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
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#define ADI_AXI_REG_RSTN_RSTN BIT(0)
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/* ADC Channel controls */
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#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
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#define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
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#define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
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#define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
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#define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
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#define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
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#define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
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#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
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(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
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ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
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ADI_AXI_REG_CHAN_CTRL_ENABLE)
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struct adi_axi_adc_state {
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struct regmap *regmap;
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struct device *dev;
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};
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static int axi_adc_enable(struct iio_backend *back)
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{
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struct adi_axi_adc_state *st = iio_backend_get_priv(back);
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int ret;
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ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,
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ADI_AXI_REG_RSTN_MMCM_RSTN);
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if (ret)
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return ret;
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fsleep(10000);
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return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,
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ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
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}
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static void axi_adc_disable(struct iio_backend *back)
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{
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struct adi_axi_adc_state *st = iio_backend_get_priv(back);
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regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0);
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}
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static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan,
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const struct iio_backend_data_fmt *data)
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{
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struct adi_axi_adc_state *st = iio_backend_get_priv(back);
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u32 val;
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if (!data->enable)
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return regmap_clear_bits(st->regmap,
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ADI_AXI_REG_CHAN_CTRL(chan),
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ADI_AXI_REG_CHAN_CTRL_FMT_EN);
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val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true);
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if (data->sign_extend)
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val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true);
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if (data->type == IIO_BACKEND_OFFSET_BINARY)
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val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true);
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return regmap_update_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
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ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val);
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}
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static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan)
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{
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struct adi_axi_adc_state *st = iio_backend_get_priv(back);
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return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
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ADI_AXI_REG_CHAN_CTRL_ENABLE);
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}
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static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan)
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{
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struct adi_axi_adc_state *st = iio_backend_get_priv(back);
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return regmap_clear_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
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ADI_AXI_REG_CHAN_CTRL_ENABLE);
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}
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static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
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struct iio_dev *indio_dev)
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{
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struct adi_axi_adc_state *st = iio_backend_get_priv(back);
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struct iio_buffer *buffer;
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const char *dma_name;
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int ret;
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if (device_property_read_string(st->dev, "dma-names", &dma_name))
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dma_name = "rx";
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buffer = iio_dmaengine_buffer_alloc(st->dev, dma_name);
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if (IS_ERR(buffer)) {
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dev_err(st->dev, "Could not get DMA buffer, %ld\n",
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PTR_ERR(buffer));
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return ERR_CAST(buffer);
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}
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indio_dev->modes |= INDIO_BUFFER_HARDWARE;
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ret = iio_device_attach_buffer(indio_dev, buffer);
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if (ret)
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return ERR_PTR(ret);
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return buffer;
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}
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static void axi_adc_free_buffer(struct iio_backend *back,
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struct iio_buffer *buffer)
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{
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iio_dmaengine_buffer_free(buffer);
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}
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static const struct regmap_config axi_adc_regmap_config = {
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.val_bits = 32,
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.reg_bits = 32,
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.reg_stride = 4,
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.max_register = 0x0800,
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};
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static const struct iio_backend_ops adi_axi_adc_generic = {
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.enable = axi_adc_enable,
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.disable = axi_adc_disable,
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.data_format_set = axi_adc_data_format_set,
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.chan_enable = axi_adc_chan_enable,
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.chan_disable = axi_adc_chan_disable,
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.request_buffer = axi_adc_request_buffer,
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.free_buffer = axi_adc_free_buffer,
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};
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static int adi_axi_adc_probe(struct platform_device *pdev)
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{
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const unsigned int *expected_ver;
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struct adi_axi_adc_state *st;
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void __iomem *base;
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unsigned int ver;
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int ret;
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st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
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if (!st)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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st->dev = &pdev->dev;
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st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&axi_adc_regmap_config);
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if (IS_ERR(st->regmap))
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return PTR_ERR(st->regmap);
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expected_ver = device_get_match_data(&pdev->dev);
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if (!expected_ver)
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return -ENODEV;
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/*
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* Force disable the core. Up to the frontend to enable us. And we can
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* still read/write registers...
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*/
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ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0);
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if (ret)
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return ret;
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ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
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if (ret)
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return ret;
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if (*expected_ver > ver) {
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dev_err(&pdev->dev,
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"IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
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ADI_AXI_PCORE_VER_MAJOR(*expected_ver),
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ADI_AXI_PCORE_VER_MINOR(*expected_ver),
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ADI_AXI_PCORE_VER_PATCH(*expected_ver),
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ADI_AXI_PCORE_VER_MAJOR(ver),
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ADI_AXI_PCORE_VER_MINOR(ver),
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ADI_AXI_PCORE_VER_PATCH(ver));
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return -ENODEV;
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}
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ret = devm_iio_backend_register(&pdev->dev, &adi_axi_adc_generic, st);
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if (ret)
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return ret;
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dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
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ADI_AXI_PCORE_VER_MAJOR(ver),
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ADI_AXI_PCORE_VER_MINOR(ver),
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ADI_AXI_PCORE_VER_PATCH(ver));
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return 0;
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}
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static unsigned int adi_axi_adc_10_0_a_info = ADI_AXI_PCORE_VER(10, 0, 'a');
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/* Match table for of_platform binding */
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static const struct of_device_id adi_axi_adc_of_match[] = {
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{ .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
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{ /* end of list */ }
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};
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MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
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static struct platform_driver adi_axi_adc_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = adi_axi_adc_of_match,
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},
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.probe = adi_axi_adc_probe,
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};
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module_platform_driver(adi_axi_adc_driver);
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MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
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MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(IIO_DMAENGINE_BUFFER);
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MODULE_IMPORT_NS(IIO_BACKEND);
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