cbd27b8ced
Interestingly enough, ppc32 had broken timekeeping for ages... It worked, but probably drifted a bit more than could be explained by the actual bad precision of the timebase calibration. We discovered that recently when somebody figured out that the common code was using CLOCK_TICK_RATE to correct the timekeeing, and ppc32 had a completely bogus value for it. This patch turns it into something saner. Probably not as good as doing something based on the actual timebase frequency precision but I'll leave that sort of math to others. This at least makes it better for the common HZ values. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
50 lines
802 B
C
50 lines
802 B
C
#ifndef _ASM_POWERPC_TIMEX_H
|
|
#define _ASM_POWERPC_TIMEX_H
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
/*
|
|
* PowerPC architecture timex specifications
|
|
*/
|
|
|
|
#include <linux/config.h>
|
|
#include <asm/cputable.h>
|
|
|
|
#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
|
|
|
|
typedef unsigned long cycles_t;
|
|
|
|
static inline cycles_t get_cycles(void)
|
|
{
|
|
cycles_t ret;
|
|
|
|
#ifdef __powerpc64__
|
|
|
|
__asm__ __volatile__("mftb %0" : "=r" (ret) : );
|
|
|
|
#else
|
|
/*
|
|
* For the "cycle" counter we use the timebase lower half.
|
|
* Currently only used on SMP.
|
|
*/
|
|
|
|
ret = 0;
|
|
|
|
__asm__ __volatile__(
|
|
"98: mftb %0\n"
|
|
"99:\n"
|
|
".section __ftr_fixup,\"a\"\n"
|
|
" .long %1\n"
|
|
" .long 0\n"
|
|
" .long 98b\n"
|
|
" .long 99b\n"
|
|
".previous"
|
|
: "=r" (ret) : "i" (CPU_FTR_601));
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
#endif /* __KERNEL__ */
|
|
#endif /* _ASM_POWERPC_TIMEX_H */
|