19f9a34f87
This implements initial support for the vsyscall page on SH. At the moment we leave it configurable due to having nommu to support from the same code base. We hook it up for the signal trampoline return at present, with more to be added later, once uClibc catches up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
300 lines
7.0 KiB
Plaintext
300 lines
7.0 KiB
Plaintext
menu "Processor selection"
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#
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# Processor families
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#
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config CPU_SH2
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bool
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select SH_WRITETHROUGH
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config CPU_SH3
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bool
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select CPU_HAS_INTEVT
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select CPU_HAS_SR_RB
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config CPU_SH4
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bool
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select CPU_HAS_INTEVT
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select CPU_HAS_SR_RB
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config CPU_SH4A
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bool
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select CPU_SH4
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config CPU_SH4AL_DSP
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bool
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select CPU_SH4A
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config CPU_SUBTYPE_ST40
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bool
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select CPU_SH4
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select CPU_HAS_INTC2_IRQ
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#
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# Processor subtypes
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#
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comment "SH-2 Processor Support"
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config CPU_SUBTYPE_SH7604
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bool "Support SH7604 processor"
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select CPU_SH2
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comment "SH-3 Processor Support"
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config CPU_SUBTYPE_SH7300
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bool "Support SH7300 processor"
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select CPU_SH3
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config CPU_SUBTYPE_SH7705
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bool "Support SH7705 processor"
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select CPU_SH3
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select CPU_HAS_PINT_IRQ
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config CPU_SUBTYPE_SH7706
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bool "Support SH7706 processor"
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select CPU_SH3
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help
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Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
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config CPU_SUBTYPE_SH7707
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bool "Support SH7707 processor"
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select CPU_SH3
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select CPU_HAS_PINT_IRQ
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help
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Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
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config CPU_SUBTYPE_SH7708
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bool "Support SH7708 processor"
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select CPU_SH3
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help
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Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
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if you have a 100 Mhz SH-3 HD6417708R CPU.
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config CPU_SUBTYPE_SH7709
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bool "Support SH7709 processor"
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select CPU_SH3
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select CPU_HAS_PINT_IRQ
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help
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Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
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config CPU_SUBTYPE_SH7710
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bool "Support SH7710 processor"
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select CPU_SH3
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help
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Select SH7710 if you have a SH3-DSP SH7710 CPU.
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comment "SH-4 Processor Support"
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config CPU_SUBTYPE_SH7750
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bool "Support SH7750 processor"
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select CPU_SH4
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help
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Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
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config CPU_SUBTYPE_SH7091
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bool "Support SH7091 processor"
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select CPU_SH4
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select CPU_SUBTYPE_SH7750
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help
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Select SH7091 if you have an SH-4 based Sega device (such as
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the Dreamcast, Naomi, and Naomi 2).
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config CPU_SUBTYPE_SH7750R
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bool "Support SH7750R processor"
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select CPU_SH4
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select CPU_SUBTYPE_SH7750
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config CPU_SUBTYPE_SH7750S
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bool "Support SH7750S processor"
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select CPU_SH4
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select CPU_SUBTYPE_SH7750
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config CPU_SUBTYPE_SH7751
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bool "Support SH7751 processor"
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select CPU_SH4
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help
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Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
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or if you have a HD6417751R CPU.
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config CPU_SUBTYPE_SH7751R
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bool "Support SH7751R processor"
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select CPU_SH4
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select CPU_SUBTYPE_SH7751
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config CPU_SUBTYPE_SH7760
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bool "Support SH7760 processor"
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select CPU_SH4
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select CPU_HAS_INTC2_IRQ
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config CPU_SUBTYPE_SH4_202
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bool "Support SH4-202 processor"
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select CPU_SH4
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comment "ST40 Processor Support"
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config CPU_SUBTYPE_ST40STB1
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bool "Support ST40STB1/ST40RA processors"
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select CPU_SUBTYPE_ST40
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help
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Select ST40STB1 if you have a ST40RA CPU.
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This was previously called the ST40STB1, hence the option name.
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config CPU_SUBTYPE_ST40GX1
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bool "Support ST40GX1 processor"
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select CPU_SUBTYPE_ST40
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help
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Select ST40GX1 if you have a ST40GX1 CPU.
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comment "SH-4A Processor Support"
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config CPU_SUBTYPE_SH7770
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bool "Support SH7770 processor"
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select CPU_SH4A
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config CPU_SUBTYPE_SH7780
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bool "Support SH7780 processor"
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select CPU_SH4A
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select CPU_HAS_INTC2_IRQ
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comment "SH4AL-DSP Processor Support"
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config CPU_SUBTYPE_SH73180
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bool "Support SH73180 processor"
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select CPU_SH4AL_DSP
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config CPU_SUBTYPE_SH7343
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bool "Support SH7343 processor"
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select CPU_SH4AL_DSP
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endmenu
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menu "Memory management options"
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config MMU
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bool "Support for memory management hardware"
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depends on !CPU_SH2
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default y
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help
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Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
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boot on these systems, this option must not be set.
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On other systems (such as the SH-3 and 4) where an MMU exists,
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turning this off will boot the kernel on these machines with the
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MMU implicitly switched off.
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config PAGE_OFFSET
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hex
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default "0x80000000" if MMU
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default "0x00000000"
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config MEMORY_START
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hex "Physical memory start address"
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default "0x08000000"
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---help---
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Computers built with Hitachi SuperH processors always
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map the ROM starting at address zero. But the processor
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does not specify the range that RAM takes.
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The physical memory (RAM) start address will be automatically
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set to 08000000. Other platforms, such as the Solution Engine
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boards typically map RAM at 0C000000.
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Tweak this only when porting to a new machine which does not
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already have a defconfig. Changing it from the known correct
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value on any of the known systems will only lead to disaster.
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config MEMORY_SIZE
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hex "Physical memory size"
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default "0x00400000"
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help
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This sets the default memory size assumed by your SH kernel. It can
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be overridden as normal by the 'mem=' argument on the kernel command
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line. If unsure, consult your board specifications or just leave it
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as 0x00400000 which was the default value before this became
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configurable.
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config 32BIT
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bool "Support 32-bit physical addressing through PMB"
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depends on CPU_SH4A && MMU
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default y
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help
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If you say Y here, physical addressing will be extended to
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32-bits through the SH-4A PMB. If this is not set, legacy
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29-bit physical addressing will be used.
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config VSYSCALL
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bool "Support vsyscall page"
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depends on MMU
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default y
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help
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This will enable support for the kernel mapping a vDSO page
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in process space, and subsequently handing down the entry point
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to the libc through the ELF auxiliary vector.
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From the kernel side this is used for the signal trampoline.
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For systems with an MMU that can afford to give up a page,
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(the default value) say Y.
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choice
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prompt "HugeTLB page size"
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depends on HUGETLB_PAGE && CPU_SH4 && MMU
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default HUGETLB_PAGE_SIZE_64K
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config HUGETLB_PAGE_SIZE_64K
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bool "64K"
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config HUGETLB_PAGE_SIZE_1MB
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bool "1MB"
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endchoice
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source "mm/Kconfig"
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endmenu
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menu "Cache configuration"
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config SH7705_CACHE_32KB
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bool "Enable 32KB cache size for SH7705"
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depends on CPU_SUBTYPE_SH7705
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default y
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config SH_DIRECT_MAPPED
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bool "Use direct-mapped caching"
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default n
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help
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Selecting this option will configure the caches to be direct-mapped,
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even if the cache supports a 2 or 4-way mode. This is useful primarily
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for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
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SH4-202, SH4-501, etc.)
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Turn this option off for platforms that do not have a direct-mapped
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cache, and you have no need to run the caches in such a configuration.
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config SH_WRITETHROUGH
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bool "Use write-through caching"
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default y if CPU_SH2
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help
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Selecting this option will configure the caches in write-through
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mode, as opposed to the default write-back configuration.
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Since there's sill some aliasing issues on SH-4, this option will
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unfortunately still require the majority of flushing functions to
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be implemented to deal with aliasing.
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If unsure, say N.
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config SH_OCRAM
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bool "Operand Cache RAM (OCRAM) support"
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help
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Selecting this option will automatically tear down the number of
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sets in the dcache by half, which in turn exposes a memory range.
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The addresses for the OC RAM base will vary according to the
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processor version. Consult vendor documentation for specifics.
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If unsure, say N.
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endmenu
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