085ae41f66
There were three changes necessary in order to allow
sparc64 to use setup-res.c:
1) Sparc64 roots the PCI I/O and MEM address space using
parent resources contained in the PCI controller structure.
I'm actually surprised no other platforms do this, especially
ones like Alpha and PPC{,64}. These resources get linked into the
iomem/ioport tree when PCI controllers are probed.
So the hierarchy looks like this:
iomem --|
PCI controller 1 MEM space --|
device 1
device 2
etc.
PCI controller 2 MEM space --|
...
ioport --|
PCI controller 1 IO space --|
...
PCI controller 2 IO space --|
...
You get the idea. The drivers/pci/setup-res.c code allocates
using plain iomem_space and ioport_space as the root, so that
wouldn't work with the above setup.
So I added a pcibios_select_root() that is used to handle this.
It uses the PCI controller struct's io_space and mem_space on
sparc64, and io{port,mem}_resource on every other platform to
keep current behavior.
2) quirk_io_region() is buggy. It takes in raw BUS view addresses
and tries to use them as a PCI resource.
pci_claim_resource() expects the resource to be fully formed when
it gets called. The sparc64 implementation would do the translation
but that's absolutely wrong, because if the same resource gets
released then re-claimed we'll adjust things twice.
So I fixed up quirk_io_region() to do the proper pcibios_bus_to_resource()
conversion before passing it on to pci_claim_resource().
3) I was mistakedly __init'ing the function methods the PCI controller
drivers provide on sparc64 to implement some parts of these
routines. This was, of course, easy to fix.
So we end up with the following, and that nasty SPARC64 makefile
ifdef in drivers/pci/Makefile is finally zapped.
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
286 lines
8.9 KiB
C
286 lines
8.9 KiB
C
#ifndef __SPARC64_PCI_H
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#define __SPARC64_PCI_H
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#ifdef __KERNEL__
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#include <linux/fs.h>
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#include <linux/mm.h>
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/* Can be used to override the logic in pci_scan_bus for skipping
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* already-configured bus numbers - to be used for buggy BIOSes
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* or architectures with incomplete PCI setup by the loader.
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*/
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#define pcibios_assign_all_busses() 0
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#define pcibios_scan_all_fns(a, b) 0
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#define PCIBIOS_MIN_IO 0UL
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#define PCIBIOS_MIN_MEM 0UL
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#define PCI_IRQ_NONE 0xffffffff
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static inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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/* Dynamic DMA mapping stuff.
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*/
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/* The PCI address space does not equal the physical memory
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* address space. The networking and block device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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#include <asm/scatterlist.h>
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struct pci_dev;
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/* Allocate and map kernel buffer using consistent mode DMA for a device.
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* hwdev should be valid struct pci_dev pointer for PCI devices.
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*/
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extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
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/* Free and unmap a consistent DMA buffer.
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* cpu_addr is what was returned from pci_alloc_consistent,
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* size must be the same as what as passed into pci_alloc_consistent,
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* and likewise dma_addr must be the same as what *dma_addrp was set to.
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*
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* References to the memory and mappings associated with cpu_addr/dma_addr
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* past this call are illegal.
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*/
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extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
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/* Map a single buffer of the indicated size for DMA in streaming mode.
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* The 32-bit bus address to use is returned.
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*
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* Once the device is given the dma address, the device owns this memory
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* until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
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*/
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extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
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/* Unmap a single streaming mode DMA translation. The dma_addr and size
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* must match what was provided for in a previous pci_map_single call. All
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* other usages are undefined.
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*
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* After this call, reads by the cpu to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
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/* No highmem on sparc64, plus we have an IOMMU, so mapping pages is easy. */
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#define pci_map_page(dev, page, off, size, dir) \
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pci_map_single(dev, (page_address(page) + (off)), size, dir)
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#define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir)
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scatter-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
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int nents, int direction);
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/* Unmap a set of streaming mode DMA translations.
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* Again, cpu read rules concerning calls here are the same as for
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* pci_unmap_single() above.
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*/
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extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
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int nhwents, int direction);
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/* Make physical memory consistent for a single
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* streaming mode DMA translation after a transfer.
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*
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* If you perform a pci_map_single() but wish to interrogate the
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* buffer using the cpu, yet do not wish to teardown the PCI dma
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* mapping, you must call this function before doing so. At the
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* next point you give the PCI dma address back to the card, you
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* must first perform a pci_dma_sync_for_device, and then the
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* device again owns the buffer.
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*/
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extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle,
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size_t size, int direction);
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static inline void
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pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle,
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size_t size, int direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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BUG_ON(direction == PCI_DMA_NONE);
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}
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/* Make physical memory consistent for a set of streaming
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* mode DMA translations after a transfer.
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*
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* The same as pci_dma_sync_single_* but for a scatter-gather list,
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* same rules and usage.
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*/
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extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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static inline void
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pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg,
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int nelems, int direction)
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{
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/* No flushing needed to sync cpu writes to the device. */
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BUG_ON(direction == PCI_DMA_NONE);
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}
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/* Return whether the given PCI device DMA address mask can
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* be supported properly. For example, if your device can
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* only drive the low 24-bits during PCI bus mastering, then
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* you would pass 0x00ffffff as the mask to this function.
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*/
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extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
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/* PCI IOMMU mapping bypass support. */
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/* PCI 64-bit addressing works for all slots on all controller
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* types on sparc64. However, it requires that the device
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* can drive enough of the 64 bits.
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*/
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#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
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#define PCI64_ADDR_BASE 0xfffc000000000000UL
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/* Usage of the pci_dac_foo interfaces is only valid if this
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* test passes.
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*/
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#define pci_dac_dma_supported(pci_dev, mask) \
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((((mask) & PCI64_REQUIRED_MASK) == PCI64_REQUIRED_MASK) ? 1 : 0)
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static inline dma64_addr_t
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pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
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{
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return (PCI64_ADDR_BASE +
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__pa(page_address(page)) + offset);
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}
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static inline struct page *
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pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
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{
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unsigned long paddr = (dma_addr & PAGE_MASK) - PCI64_ADDR_BASE;
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return virt_to_page(__va(paddr));
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}
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static inline unsigned long
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pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
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{
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return (dma_addr & ~PAGE_MASK);
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}
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static inline void
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pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
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{
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/* DAC cycle addressing does not make use of the
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* PCI controller's streaming cache, so nothing to do.
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*/
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}
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static inline void
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pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
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{
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/* DAC cycle addressing does not make use of the
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* PCI controller's streaming cache, so nothing to do.
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*/
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}
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#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
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static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
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{
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return (dma_addr == PCI_DMA_ERROR_CODE);
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}
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_BOUNDARY;
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*strategy_parameter = cacheline_size;
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}
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#endif
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/* Return the index of the PCI controller for device PDEV. */
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extern int pci_domain_nr(struct pci_bus *bus);
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return 1;
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}
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/* Platform support for /proc/bus/pci/X/Y mmap()s. */
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#define HAVE_PCI_MMAP
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#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
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#define get_pci_unmapped_area get_fb_unmapped_area
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extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state,
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int write_combine);
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/* Platform specific MWI support. */
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#define HAVE_ARCH_PCI_MWI
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extern int pcibios_prep_mwi(struct pci_dev *dev);
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extern void
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pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res);
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extern void
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pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
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static inline void pcibios_add_platform_entries(struct pci_dev *dev)
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{
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}
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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return PCI_IRQ_NONE;
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}
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#endif /* __KERNEL__ */
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#endif /* __SPARC64_PCI_H */
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