e4ee69c8c1
The Power Management Unit on PowerMacs is very sensitive to timeouts during async message exchanges. It uses rather crude protocol based on a shift register with an interrupt and is almost continuously exchanging messages with the host CPU on laptops. This patch adds a routine to the open_pic driver to be able to select a PMU driver so that it bumps it's interrupt priority to above the normal level. This will allow PMU interrupts to occur while another interrupt is pending, and thus reduce the risk of machine beeing abruptly shutdown by the PMU due to a timeout in PMU communication caused by excessive interrupt latency. The problem is very rare, and usually just doesn't happen, but it is still useful to make things even more robust. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/*
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* include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
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*
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* Copyright (C) 1997 Geert Uytterhoeven
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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*/
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#ifndef _PPC_KERNEL_OPEN_PIC_H
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#define _PPC_KERNEL_OPEN_PIC_H
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#include <linux/config.h>
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#include <linux/irq.h>
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#define OPENPIC_SIZE 0x40000
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/*
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* Non-offset'ed vector numbers
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*/
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#define OPENPIC_VEC_TIMER 110 /* and up */
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#define OPENPIC_VEC_IPI 118 /* and up */
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#define OPENPIC_VEC_SPURIOUS 255
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/* Priorities */
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#define OPENPIC_PRIORITY_IPI_BASE 10
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#define OPENPIC_PRIORITY_DEFAULT 4
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#define OPENPIC_PRIORITY_NMI 9
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/* OpenPIC IRQ controller structure */
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extern struct hw_interrupt_type open_pic;
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/* OpenPIC IPI controller structure */
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#ifdef CONFIG_SMP
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extern struct hw_interrupt_type open_pic_ipi;
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#endif /* CONFIG_SMP */
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extern u_int OpenPIC_NumInitSenses;
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extern u_char *OpenPIC_InitSenses;
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extern void __iomem * OpenPIC_Addr;
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extern int epic_serial_mode;
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/* Exported functions */
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extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
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extern void openpic_init(int linux_irq_offset);
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extern void openpic_init_nmi_irq(u_int irq);
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extern void openpic_set_irq_priority(u_int irq, u_int pri);
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extern void openpic_hookup_cascade(u_int irq, char *name,
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int (*cascade_fn)(struct pt_regs *));
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extern u_int openpic_irq(void);
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extern void openpic_eoi(void);
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extern void openpic_request_IPIs(void);
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extern void do_openpic_setup_cpu(void);
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extern int openpic_get_irq(struct pt_regs *regs);
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extern void openpic_reset_processor_phys(u_int cpumask);
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extern void openpic_setup_ISU(int isu_num, unsigned long addr);
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extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
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extern void smp_openpic_message_pass(int target, int msg, unsigned long data,
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int wait);
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extern void openpic_set_k2_cascade(int irq);
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extern void openpic_set_priority(u_int pri);
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extern u_int openpic_get_priority(void);
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extern inline int openpic_to_irq(int irq)
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{
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/* IRQ 0 usually means 'disabled'.. don't mess with it
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* exceptions to this (sandpoint maybe?)
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* shouldn't use openpic_to_irq
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*/
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if (irq != 0){
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return irq += NUM_8259_INTERRUPTS;
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} else {
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return 0;
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}
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}
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/* Support for second openpic on G5 macs */
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// FIXME: To be replaced by sane cascaded controller management */
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#define PMAC_OPENPIC2_OFFSET 128
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#define OPENPIC2_VEC_TIMER 110 /* and up */
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#define OPENPIC2_VEC_IPI 118 /* and up */
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#define OPENPIC2_VEC_SPURIOUS 127
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extern void* OpenPIC2_Addr;
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/* Exported functions */
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extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
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extern void openpic2_init(int linux_irq_offset);
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extern void openpic2_init_nmi_irq(u_int irq);
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extern u_int openpic2_irq(void);
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extern void openpic2_eoi(void);
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extern int openpic2_get_irq(struct pt_regs *regs);
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extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
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#endif /* _PPC_KERNEL_OPEN_PIC_H */
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