1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
464 lines
12 KiB
C
464 lines
12 KiB
C
/*
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* ibm_ocp_mal.c
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*
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* Armin Kuster akuster@mvista.com
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* Juen, 2002
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*
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* Copyright 2002 MontaVista Softare Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/netdevice.h>
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#include <linux/init.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/ocp.h>
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#include "ibm_emac_mal.h"
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// Locking: Should we share a lock with the client ? The client could provide
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// a lock pointer (optionally) in the commac structure... I don't think this is
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// really necessary though
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/* This lock protects the commac list. On today UP implementations, it's
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* really only used as IRQ protection in mal_{register,unregister}_commac()
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*/
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static DEFINE_RWLOCK(mal_list_lock);
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int mal_register_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
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{
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unsigned long flags;
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write_lock_irqsave(&mal_list_lock, flags);
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/* Don't let multiple commacs claim the same channel */
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if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
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(mal->rx_chan_mask & commac->rx_chan_mask)) {
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write_unlock_irqrestore(&mal_list_lock, flags);
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return -EBUSY;
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}
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mal->tx_chan_mask |= commac->tx_chan_mask;
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mal->rx_chan_mask |= commac->rx_chan_mask;
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list_add(&commac->list, &mal->commac);
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write_unlock_irqrestore(&mal_list_lock, flags);
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return 0;
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}
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int mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
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{
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unsigned long flags;
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write_lock_irqsave(&mal_list_lock, flags);
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mal->tx_chan_mask &= ~commac->tx_chan_mask;
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mal->rx_chan_mask &= ~commac->rx_chan_mask;
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list_del_init(&commac->list);
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write_unlock_irqrestore(&mal_list_lock, flags);
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return 0;
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}
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int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size)
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{
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switch (channel) {
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case 0:
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set_mal_dcrn(mal, DCRN_MALRCBS0, size);
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break;
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#ifdef DCRN_MALRCBS1
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case 1:
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set_mal_dcrn(mal, DCRN_MALRCBS1, size);
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break;
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#endif
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#ifdef DCRN_MALRCBS2
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case 2:
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set_mal_dcrn(mal, DCRN_MALRCBS2, size);
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break;
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#endif
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#ifdef DCRN_MALRCBS3
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case 3:
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set_mal_dcrn(mal, DCRN_MALRCBS3, size);
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break;
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#endif
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default:
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return -EINVAL;
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}
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return 0;
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}
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static irqreturn_t mal_serr(int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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unsigned long mal_error;
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/*
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* This SERR applies to one of the devices on the MAL, here we charge
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* it against the first EMAC registered for the MAL.
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*/
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mal_error = get_mal_dcrn(mal, DCRN_MALESR);
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printk(KERN_ERR "%s: System Error (MALESR=%lx)\n",
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"MAL" /* FIXME: get the name right */ , mal_error);
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/* FIXME: decipher error */
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/* DIXME: distribute to commacs, if possible */
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/* Clear the error status register */
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set_mal_dcrn(mal, DCRN_MALESR, mal_error);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_txeob(int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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struct list_head *l;
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unsigned long isr;
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isr = get_mal_dcrn(mal, DCRN_MALTXEOBISR);
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set_mal_dcrn(mal, DCRN_MALTXEOBISR, isr);
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read_lock(&mal_list_lock);
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list_for_each(l, &mal->commac) {
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struct mal_commac *mc = list_entry(l, struct mal_commac, list);
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if (isr & mc->tx_chan_mask) {
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mc->ops->txeob(mc->dev, isr & mc->tx_chan_mask);
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}
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}
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read_unlock(&mal_list_lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_rxeob(int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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struct list_head *l;
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unsigned long isr;
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isr = get_mal_dcrn(mal, DCRN_MALRXEOBISR);
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set_mal_dcrn(mal, DCRN_MALRXEOBISR, isr);
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read_lock(&mal_list_lock);
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list_for_each(l, &mal->commac) {
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struct mal_commac *mc = list_entry(l, struct mal_commac, list);
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if (isr & mc->rx_chan_mask) {
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mc->ops->rxeob(mc->dev, isr & mc->rx_chan_mask);
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}
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}
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read_unlock(&mal_list_lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_txde(int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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struct list_head *l;
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unsigned long deir;
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deir = get_mal_dcrn(mal, DCRN_MALTXDEIR);
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/* FIXME: print which MAL correctly */
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printk(KERN_WARNING "%s: Tx descriptor error (MALTXDEIR=%lx)\n",
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"MAL", deir);
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read_lock(&mal_list_lock);
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list_for_each(l, &mal->commac) {
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struct mal_commac *mc = list_entry(l, struct mal_commac, list);
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if (deir & mc->tx_chan_mask) {
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mc->ops->txde(mc->dev, deir & mc->tx_chan_mask);
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}
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}
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read_unlock(&mal_list_lock);
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return IRQ_HANDLED;
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}
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/*
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* This interrupt should be very rare at best. This occurs when
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* the hardware has a problem with the receive descriptors. The manual
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* states that it occurs when the hardware cannot the receive descriptor
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* empty bit is not set. The recovery mechanism will be to
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* traverse through the descriptors, handle any that are marked to be
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* handled and reinitialize each along the way. At that point the driver
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* will be restarted.
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*/
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static irqreturn_t mal_rxde(int irq, void *dev_instance, struct pt_regs *regs)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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struct list_head *l;
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unsigned long deir;
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deir = get_mal_dcrn(mal, DCRN_MALRXDEIR);
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/*
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* This really is needed. This case encountered in stress testing.
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*/
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if (deir == 0)
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return IRQ_HANDLED;
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/* FIXME: print which MAL correctly */
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printk(KERN_WARNING "%s: Rx descriptor error (MALRXDEIR=%lx)\n",
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"MAL", deir);
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read_lock(&mal_list_lock);
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list_for_each(l, &mal->commac) {
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struct mal_commac *mc = list_entry(l, struct mal_commac, list);
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if (deir & mc->rx_chan_mask) {
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mc->ops->rxde(mc->dev, deir & mc->rx_chan_mask);
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}
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}
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read_unlock(&mal_list_lock);
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return IRQ_HANDLED;
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}
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static int __init mal_probe(struct ocp_device *ocpdev)
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{
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struct ibm_ocp_mal *mal = NULL;
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struct ocp_func_mal_data *maldata;
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int err = 0;
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maldata = (struct ocp_func_mal_data *)ocpdev->def->additions;
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if (maldata == NULL) {
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printk(KERN_ERR "mal%d: Missing additional datas !\n",
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ocpdev->def->index);
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return -ENODEV;
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}
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mal = kmalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL);
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if (mal == NULL) {
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printk(KERN_ERR
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"mal%d: Out of memory allocating MAL structure !\n",
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ocpdev->def->index);
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return -ENOMEM;
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}
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memset(mal, 0, sizeof(*mal));
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switch (ocpdev->def->index) {
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case 0:
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mal->dcrbase = DCRN_MAL_BASE;
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break;
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#ifdef DCRN_MAL1_BASE
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case 1:
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mal->dcrbase = DCRN_MAL1_BASE;
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break;
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#endif
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default:
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BUG();
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}
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/**************************/
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INIT_LIST_HEAD(&mal->commac);
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set_mal_dcrn(mal, DCRN_MALRXCARR, 0xFFFFFFFF);
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set_mal_dcrn(mal, DCRN_MALTXCARR, 0xFFFFFFFF);
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set_mal_dcrn(mal, DCRN_MALCR, MALCR_MMSR); /* 384 */
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/* FIXME: Add delay */
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/* Set the MAL configuration register */
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set_mal_dcrn(mal, DCRN_MALCR,
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MALCR_PLBB | MALCR_OPBBL | MALCR_LEA |
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MALCR_PLBLT_DEFAULT);
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/* It would be nice to allocate buffers separately for each
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* channel, but we can't because the channels share the upper
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* 13 bits of address lines. Each channels buffer must also
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* be 4k aligned, so we allocate 4k for each channel. This is
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* inefficient FIXME: do better, if possible */
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mal->tx_virt_addr = dma_alloc_coherent(&ocpdev->dev,
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MAL_DT_ALIGN *
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maldata->num_tx_chans,
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&mal->tx_phys_addr, GFP_KERNEL);
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if (mal->tx_virt_addr == NULL) {
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printk(KERN_ERR
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"mal%d: Out of memory allocating MAL descriptors !\n",
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ocpdev->def->index);
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err = -ENOMEM;
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goto fail;
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}
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/* God, oh, god, I hate DCRs */
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set_mal_dcrn(mal, DCRN_MALTXCTP0R, mal->tx_phys_addr);
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#ifdef DCRN_MALTXCTP1R
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if (maldata->num_tx_chans > 1)
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set_mal_dcrn(mal, DCRN_MALTXCTP1R,
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mal->tx_phys_addr + MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP1R */
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#ifdef DCRN_MALTXCTP2R
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if (maldata->num_tx_chans > 2)
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set_mal_dcrn(mal, DCRN_MALTXCTP2R,
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mal->tx_phys_addr + 2 * MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP2R */
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#ifdef DCRN_MALTXCTP3R
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if (maldata->num_tx_chans > 3)
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set_mal_dcrn(mal, DCRN_MALTXCTP3R,
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mal->tx_phys_addr + 3 * MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP3R */
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#ifdef DCRN_MALTXCTP4R
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if (maldata->num_tx_chans > 4)
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set_mal_dcrn(mal, DCRN_MALTXCTP4R,
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mal->tx_phys_addr + 4 * MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP4R */
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#ifdef DCRN_MALTXCTP5R
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if (maldata->num_tx_chans > 5)
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set_mal_dcrn(mal, DCRN_MALTXCTP5R,
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mal->tx_phys_addr + 5 * MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP5R */
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#ifdef DCRN_MALTXCTP6R
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if (maldata->num_tx_chans > 6)
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set_mal_dcrn(mal, DCRN_MALTXCTP6R,
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mal->tx_phys_addr + 6 * MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP6R */
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#ifdef DCRN_MALTXCTP7R
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if (maldata->num_tx_chans > 7)
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set_mal_dcrn(mal, DCRN_MALTXCTP7R,
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mal->tx_phys_addr + 7 * MAL_DT_ALIGN);
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#endif /* DCRN_MALTXCTP7R */
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mal->rx_virt_addr = dma_alloc_coherent(&ocpdev->dev,
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MAL_DT_ALIGN *
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maldata->num_rx_chans,
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&mal->rx_phys_addr, GFP_KERNEL);
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set_mal_dcrn(mal, DCRN_MALRXCTP0R, mal->rx_phys_addr);
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#ifdef DCRN_MALRXCTP1R
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if (maldata->num_rx_chans > 1)
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set_mal_dcrn(mal, DCRN_MALRXCTP1R,
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mal->rx_phys_addr + MAL_DT_ALIGN);
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#endif /* DCRN_MALRXCTP1R */
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#ifdef DCRN_MALRXCTP2R
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if (maldata->num_rx_chans > 2)
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set_mal_dcrn(mal, DCRN_MALRXCTP2R,
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mal->rx_phys_addr + 2 * MAL_DT_ALIGN);
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#endif /* DCRN_MALRXCTP2R */
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#ifdef DCRN_MALRXCTP3R
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if (maldata->num_rx_chans > 3)
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set_mal_dcrn(mal, DCRN_MALRXCTP3R,
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mal->rx_phys_addr + 3 * MAL_DT_ALIGN);
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#endif /* DCRN_MALRXCTP3R */
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err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal);
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if (err)
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goto fail;
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err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE ", mal);
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if (err)
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goto fail;
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err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
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if (err)
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goto fail;
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err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
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if (err)
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goto fail;
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err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
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if (err)
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goto fail;
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set_mal_dcrn(mal, DCRN_MALIER,
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MALIER_DE | MALIER_NE | MALIER_TE |
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MALIER_OPBE | MALIER_PLBE);
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/* Advertise me to the rest of the world */
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ocp_set_drvdata(ocpdev, mal);
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printk(KERN_INFO "mal%d: Initialized, %d tx channels, %d rx channels\n",
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ocpdev->def->index, maldata->num_tx_chans,
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maldata->num_rx_chans);
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return 0;
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fail:
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/* FIXME: dispose requested IRQs ! */
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if (err && mal)
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kfree(mal);
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return err;
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}
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static void __exit mal_remove(struct ocp_device *ocpdev)
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{
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struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev);
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struct ocp_func_mal_data *maldata = ocpdev->def->additions;
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BUG_ON(!maldata);
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ocp_set_drvdata(ocpdev, NULL);
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/* FIXME: shut down the MAL, deal with dependency with emac */
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free_irq(maldata->serr_irq, mal);
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free_irq(maldata->txde_irq, mal);
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free_irq(maldata->txeob_irq, mal);
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free_irq(maldata->rxde_irq, mal);
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free_irq(maldata->rxeob_irq, mal);
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if (mal->tx_virt_addr)
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dma_free_coherent(&ocpdev->dev,
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MAL_DT_ALIGN * maldata->num_tx_chans,
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mal->tx_virt_addr, mal->tx_phys_addr);
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if (mal->rx_virt_addr)
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dma_free_coherent(&ocpdev->dev,
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MAL_DT_ALIGN * maldata->num_rx_chans,
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mal->rx_virt_addr, mal->rx_phys_addr);
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kfree(mal);
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}
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/* Structure for a device driver */
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static struct ocp_device_id mal_ids[] = {
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{.vendor = OCP_ANY_ID,.function = OCP_FUNC_MAL},
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{.vendor = OCP_VENDOR_INVALID}
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};
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static struct ocp_driver mal_driver = {
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.name = "mal",
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.id_table = mal_ids,
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.probe = mal_probe,
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.remove = mal_remove,
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};
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static int __init init_mals(void)
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{
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int rc;
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rc = ocp_register_driver(&mal_driver);
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if (rc < 0) {
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ocp_unregister_driver(&mal_driver);
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return -ENODEV;
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}
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return 0;
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}
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static void __exit exit_mals(void)
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{
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ocp_unregister_driver(&mal_driver);
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}
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module_init(init_mals);
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module_exit(exit_mals);
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