1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
417 lines
10 KiB
C
417 lines
10 KiB
C
/*
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* linux/arch/alpha/kernel/core_irongate.c
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*
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* Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
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*
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* Copyright (C) 1999 Alpha Processor, Inc.,
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* (David Daniel, Stig Telfer, Soohoon Lee)
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*
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* Code common to all IRONGATE core logic chips.
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*/
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#define __EXTERN_INLINE inline
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#include <asm/io.h>
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#include <asm/core_irongate.h>
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#undef __EXTERN_INLINE
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/initrd.h>
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#include <linux/bootmem.h>
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#include <asm/ptrace.h>
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#include <asm/pci.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "pci_impl.h"
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/*
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* BIOS32-style PCI interface:
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*/
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBG_CFG(args) printk args
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#else
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# define DBG_CFG(args)
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#endif
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igcsr32 *IronECC;
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address accordingly. It is therefore not safe
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* to have concurrent invocations to configuration space access
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* routines, but there really shouldn't be any need for this.
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*
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* addr[31:24] reserved
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* addr[23:16] bus number (8 bits = 128 possible buses)
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* addr[15:11] Device number (5 bits)
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* addr[10: 8] function number
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* addr[ 7: 2] register number
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*
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* For IRONGATE:
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* if (bus = addr[23:16]) == 0
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* then
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* type 0 config cycle:
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* addr_on_pci[31:11] = id selection for device = addr[15:11]
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* addr_on_pci[10: 2] = addr[10: 2] ???
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* addr_on_pci[ 1: 0] = 00
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* else
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* type 1 config cycle (pass on with no decoding):
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* addr_on_pci[31:24] = 0
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* addr_on_pci[23: 2] = addr[23: 2]
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* addr_on_pci[ 1: 0] = 01
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* fi
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., SCSI and Ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, unsigned char *type1)
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{
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unsigned long addr;
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u8 bus = pbus->number;
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DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
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"pci_addr=0x%p, type1=0x%p)\n",
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bus, device_fn, where, pci_addr, type1));
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*type1 = (bus != 0);
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addr = (bus << 16) | (device_fn << 8) | where;
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addr |= IRONGATE_CONF;
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*pci_addr = addr;
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DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
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return 0;
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}
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static int
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irongate_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr;
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unsigned char type1;
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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*value = __kernel_ldbu(*(vucp)addr);
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break;
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case 2:
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*value = __kernel_ldwu(*(vusp)addr);
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break;
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case 4:
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*value = *(vuip)addr;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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irongate_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr;
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unsigned char type1;
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if (mk_conf_addr(bus, devfn, where, &addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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__kernel_stb(value, *(vucp)addr);
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mb();
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__kernel_ldbu(*(vucp)addr);
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break;
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case 2:
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__kernel_stw(value, *(vusp)addr);
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mb();
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__kernel_ldwu(*(vusp)addr);
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break;
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case 4:
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*(vuip)addr = value;
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mb();
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*(vuip)addr;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops irongate_pci_ops =
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{
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.read = irongate_read_config,
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.write = irongate_write_config,
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};
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int
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irongate_pci_clr_err(void)
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{
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unsigned int nmi_ctl=0;
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unsigned int IRONGATE_jd;
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again:
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IRONGATE_jd = IRONGATE0->stat_cmd;
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printk("Iron stat_cmd %x\n", IRONGATE_jd);
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IRONGATE0->stat_cmd = IRONGATE_jd; /* write again clears error bits */
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mb();
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IRONGATE_jd = IRONGATE0->stat_cmd; /* re-read to force write */
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IRONGATE_jd = *IronECC;
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printk("Iron ECC %x\n", IRONGATE_jd);
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*IronECC = IRONGATE_jd; /* write again clears error bits */
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mb();
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IRONGATE_jd = *IronECC; /* re-read to force write */
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/* Clear ALI NMI */
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nmi_ctl = inb(0x61);
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nmi_ctl |= 0x0c;
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outb(nmi_ctl, 0x61);
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nmi_ctl &= ~0x0c;
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outb(nmi_ctl, 0x61);
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IRONGATE_jd = *IronECC;
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if (IRONGATE_jd & 0x300) goto again;
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return 0;
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}
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#define IRONGATE_3GB 0xc0000000UL
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/* On Albacore (aka UP1500) with 4Gb of RAM we have to reserve some
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memory for PCI. At this point we just reserve memory above 3Gb. Most
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of this memory will be freed after PCI setup is done. */
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static void __init
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albacore_init_arch(void)
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{
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unsigned long memtop = max_low_pfn << PAGE_SHIFT;
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unsigned long pci_mem = (memtop + 0x1000000UL) & ~0xffffffUL;
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struct percpu_struct *cpu;
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int pal_rev, pal_var;
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cpu = (struct percpu_struct*)((char*)hwrpb + hwrpb->processor_offset);
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pal_rev = cpu->pal_revision & 0xffff;
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pal_var = (cpu->pal_revision >> 16) & 0xff;
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/* Consoles earlier than A5.6-18 (OSF PALcode v1.62-2) set up
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the CPU incorrectly (leave speculative stores enabled),
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which causes memory corruption under certain conditions.
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Issue a warning for such consoles. */
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if (alpha_using_srm &&
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(pal_rev < 0x13e || (pal_rev == 0x13e && pal_var < 2)))
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printk(KERN_WARNING "WARNING! Upgrade to SRM A5.6-19 "
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"or later\n");
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if (pci_mem > IRONGATE_3GB)
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pci_mem = IRONGATE_3GB;
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IRONGATE0->pci_mem = pci_mem;
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alpha_mv.min_mem_address = pci_mem;
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if (memtop > pci_mem) {
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#ifdef CONFIG_BLK_DEV_INITRD
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extern unsigned long initrd_start, initrd_end;
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extern void *move_initrd(unsigned long);
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/* Move the initrd out of the way. */
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if (initrd_end && __pa(initrd_end) > pci_mem) {
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unsigned long size;
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size = initrd_end - initrd_start;
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free_bootmem_node(NODE_DATA(0), __pa(initrd_start),
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PAGE_ALIGN(size));
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if (!move_initrd(pci_mem))
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printk("irongate_init_arch: initrd too big "
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"(%ldK)\ndisabling initrd\n",
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size / 1024);
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}
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#endif
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reserve_bootmem_node(NODE_DATA(0), pci_mem, memtop - pci_mem);
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printk("irongate_init_arch: temporarily reserving "
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"region %08lx-%08lx for PCI\n", pci_mem, memtop - 1);
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}
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}
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static void __init
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irongate_setup_agp(void)
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{
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/* Disable the GART window. AGPGART doesn't work due to yet
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unresolved memory coherency issues... */
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IRONGATE0->agpva = IRONGATE0->agpva & ~0xf;
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alpha_agpgart_size = 0;
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}
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void __init
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irongate_init_arch(void)
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{
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struct pci_controller *hose;
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int amd761 = (IRONGATE0->dev_vendor >> 16) > 0x7006; /* Albacore? */
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IronECC = amd761 ? &IRONGATE0->bacsr54_eccms761 : &IRONGATE0->dramms;
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irongate_pci_clr_err();
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if (amd761)
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albacore_init_arch();
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irongate_setup_agp();
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/*
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* Create our single hose.
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*/
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pci_isa_hose = hose = alloc_pci_controller();
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hose->io_space = &ioport_resource;
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hose->mem_space = &iomem_resource;
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hose->index = 0;
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/* This is for userland consumption. For some reason, the 40-bit
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PIO bias that we use in the kernel through KSEG didn't work for
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the page table based user mappings. So make sure we get the
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43-bit PIO bias. */
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hose->sparse_mem_base = 0;
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hose->sparse_io_base = 0;
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hose->dense_mem_base
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= (IRONGATE_MEM & 0xffffffffffUL) | 0x80000000000UL;
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hose->dense_io_base
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= (IRONGATE_IO & 0xffffffffffUL) | 0x80000000000UL;
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hose->sg_isa = hose->sg_pci = NULL;
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__direct_map_base = 0;
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__direct_map_size = 0xffffffff;
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}
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/*
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* IO map and AGP support
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*/
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#include <linux/vmalloc.h>
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#include <linux/agp_backend.h>
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#include <linux/agpgart.h>
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#include <asm/pgalloc.h>
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#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
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#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr))
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#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
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#define GET_GATT(addr) (gatt_pages[GET_PAGE_DIR_IDX(addr)])
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void __iomem *
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irongate_ioremap(unsigned long addr, unsigned long size)
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{
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struct vm_struct *area;
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unsigned long vaddr;
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unsigned long baddr, last;
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u32 *mmio_regs, *gatt_pages, *cur_gatt, pte;
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unsigned long gart_bus_addr;
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if (!alpha_agpgart_size)
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return (void __iomem *)(addr + IRONGATE_MEM);
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gart_bus_addr = (unsigned long)IRONGATE0->bar0 &
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PCI_BASE_ADDRESS_MEM_MASK;
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/*
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* Check for within the AGP aperture...
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*/
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do {
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/*
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* Check the AGP area
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*/
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if (addr >= gart_bus_addr && addr + size - 1 <
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gart_bus_addr + alpha_agpgart_size)
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break;
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/*
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* Not found - assume legacy ioremap
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*/
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return (void __iomem *)(addr + IRONGATE_MEM);
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} while(0);
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mmio_regs = (u32 *)(((unsigned long)IRONGATE0->bar1 &
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PCI_BASE_ADDRESS_MEM_MASK) + IRONGATE_MEM);
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gatt_pages = (u32 *)(phys_to_virt(mmio_regs[1])); /* FIXME */
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/*
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* Adjust the limits (mappings must be page aligned)
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*/
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if (addr & ~PAGE_MASK) {
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printk("AGP ioremap failed... addr not page aligned (0x%lx)\n",
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addr);
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return (void __iomem *)(addr + IRONGATE_MEM);
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}
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last = addr + size - 1;
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size = PAGE_ALIGN(last) - addr;
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#if 0
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printk("irongate_ioremap(0x%lx, 0x%lx)\n", addr, size);
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printk("irongate_ioremap: gart_bus_addr 0x%lx\n", gart_bus_addr);
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printk("irongate_ioremap: gart_aper_size 0x%lx\n", gart_aper_size);
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printk("irongate_ioremap: mmio_regs %p\n", mmio_regs);
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printk("irongate_ioremap: gatt_pages %p\n", gatt_pages);
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for(baddr = addr; baddr <= last; baddr += PAGE_SIZE)
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{
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cur_gatt = phys_to_virt(GET_GATT(baddr) & ~1);
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pte = cur_gatt[GET_GATT_OFF(baddr)] & ~1;
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printk("irongate_ioremap: cur_gatt %p pte 0x%x\n",
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cur_gatt, pte);
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}
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#endif
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/*
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* Map it
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*/
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area = get_vm_area(size, VM_IOREMAP);
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if (!area) return NULL;
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for(baddr = addr, vaddr = (unsigned long)area->addr;
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baddr <= last;
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baddr += PAGE_SIZE, vaddr += PAGE_SIZE)
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{
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cur_gatt = phys_to_virt(GET_GATT(baddr) & ~1);
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pte = cur_gatt[GET_GATT_OFF(baddr)] & ~1;
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if (__alpha_remap_area_pages(vaddr,
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pte, PAGE_SIZE, 0)) {
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printk("AGP ioremap: FAILED to map...\n");
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vfree(area->addr);
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return NULL;
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}
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}
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flush_tlb_all();
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vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
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#if 0
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printk("irongate_ioremap(0x%lx, 0x%lx) returning 0x%lx\n",
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addr, size, vaddr);
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#endif
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return (void __iomem *)vaddr;
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}
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void
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irongate_iounmap(volatile void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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if (((long)addr >> 41) == -2)
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return; /* kseg map, nothing to do */
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if (addr)
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return vfree((void *)(PAGE_MASK & addr));
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}
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