cb09f540a1
Changes necessary to make the sub-arch split complete. Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
105 lines
3.8 KiB
C
105 lines
3.8 KiB
C
/* $Id: etraxgpio.h,v 1.8 2002/06/17 15:53:07 johana Exp $ */
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/*
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* The following devices are accessable using this driver using
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* GPIO_MAJOR (120) and a couple of minor numbers:
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* For ETRAX 100LX (ARCH_V10):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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* /dev/gpiog minor 3
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g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
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g1-g7 and g25-g31 is both input and outputs but on different pins
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Also note that some bits change pins depending on what interfaces
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are enabled.
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*
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*
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* For ETRAX FS (ARCH_V32):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
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* /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction
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* /dev/gpiod minor 3, 18 bit GPIO, each bit can change direction
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* /dev/gpioe minor 4, 18 bit GPIO, each bit can change direction
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* /dev/leds minor 5, Access to leds depending on kernelconfig
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*
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*/
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#ifndef _ASM_ETRAXGPIO_H
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#define _ASM_ETRAXGPIO_H
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#include <linux/config.h>
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/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
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#ifdef CONFIG_ETRAX_ARCH_V10
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_G 3
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#define GPIO_MINOR_LAST 3
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#endif
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#ifdef CONFIG_ETRAX_ARCH_V32
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_C 3
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#define GPIO_MINOR_D 4
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#define GPIO_MINOR_E 5
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#define GPIO_MINOR_LAST 5
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#endif
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/* supported ioctl _IOC_NR's */
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#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
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#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */
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#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */
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/* the alarm is waited for by select() */
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#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */
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#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */
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#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */
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/* LED ioctl */
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#define IO_LEDACTIVE_SET 0x7 /* set active led
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* 0=off, 1=green, 2=red, 3=yellow */
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/* GPIO direction ioctl's */
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#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */
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#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
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returns mask with current inputs (obsolete) */
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#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output,
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returns mask with current outputs (obsolete)*/
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/* LED ioctl extended */
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#define IO_LED_SETBIT 0xB
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#define IO_LED_CLRBIT 0xC
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/* SHUTDOWN ioctl */
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#define IO_SHUTDOWN 0xD
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#define IO_GET_PWR_BT 0xE
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/* Bit toggling in driver settings */
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/* bit set in low byte0 is CLK mask (0x00FF),
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bit set in byte1 is DATA mask (0xFF00)
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msb, data_mask[7:0] , clk_mask[7:0]
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*/
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#define IO_CFG_WRITE_MODE 0xF
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#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
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( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
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/* The following 4 ioctl's take a pointer as argument and handles
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* 32 bit ports (port G) properly.
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* These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
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*/
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#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
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#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
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#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input,
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* *arg updated with current input pins.
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*/
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#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
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* *arg updated with current output pins.
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*/
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#endif
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