59d1ff3bfb
save_and_disable_irqs does not need to use mov + msr (which was introduced to work around a documentation bug which was propagated into binutils.) Use msr with an immediate constant, and if we're building for ARMv6 or later, use the new CPSID instruction. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
121 lines
2.7 KiB
C
121 lines
2.7 KiB
C
/*
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* linux/include/asm-arm/assembler.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#include <asm/ptrace.h>
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define pull lsr
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#define push lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define pull lsl
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#define push lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if __LINUX_ARM_ARCH__ >= 5
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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#define MODE_USR USR_MODE
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#define MODE_FIQ FIQ_MODE
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#define MODE_IRQ IRQ_MODE
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#define MODE_SVC SVC_MODE
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#define DEFAULT_FIQ MODE_FIQ
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/*
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* LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
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*/
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#ifdef __STDC__
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#define LOADREGS(cond, base, reglist...)\
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ldm##cond base,reglist
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#else
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#define LOADREGS(cond, base, reglist...)\
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ldm/**/cond base,reglist
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#endif
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/*
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* Build a return instruction for this processor type.
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*/
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#define RETINSTR(instr, regs...)\
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instr regs
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/*
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* Save the current IRQ state and disable IRQs. Note that this macro
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* assumes FIQs are enabled, and that the processor is in SVC mode.
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*/
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.macro save_and_disable_irqs, oldcpsr
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mrs \oldcpsr, cpsr
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#if __LINUX_ARM_ARCH__ >= 6
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cpsid i
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#else
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msr cpsr_c, #PSR_I_BIT | MODE_SVC
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#endif
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.endm
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/*
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* Restore interrupt state previously stored in a register. We don't
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* guarantee that this will preserve the flags.
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*/
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.macro restore_irqs, oldcpsr
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msr cpsr_c, \oldcpsr
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.endm
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/*
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* These two are used to save LR/restore PC over a user-based access.
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* The old 26-bit architecture requires that we do. On 32-bit
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* architecture, we can safely ignore this requirement.
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*/
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.macro save_lr
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.endm
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.macro restore_pc
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mov pc, lr
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.endm
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#define USER(x...) \
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9999: x; \
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.section __ex_table,"a"; \
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.align 3; \
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.long 9999b,9001f; \
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.previous
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