1626aeb881
The intention of using port_mask in SFF init helpers was to eventually support exoctic configurations such as combination of legacy and native port on the same controller. This never became actually necessary and the related code always has been subtly broken one way or the other. Now that new init model is in place, there is no reason to make common helpers capable of handling all corner cases. Exotic cases can simply dealt within LLDs as necessary. This patch removes port_mask handling in SFF init helpers. SFF init helpers don't take n_ports argument and interpret it into port_mask anymore. All information is carried via port_info. n_ports argument is dropped and always two ports are allocated. LLD can tell SFF to skip certain port by marking it dummy. Note that SFF code has been treating unuvailable ports this way for a long time until recent breakage fix from Linus and is consistent with how other drivers handle with unavailable ports. This fixes 1-port legacy host handling still broken after the recent native mode fix and simplifies SFF init logic. The following changes are made... * ata_pci_init_native_host() and ata_init_legacy_host() both now try to initialized whatever they can and mark failed ports dummy. They return 0 if any port is successfully initialized. * ata_pci_prepare_native_host() and ata_pci_init_one() now doesn't take n_ports argument. All info should be specified via port_info array. Always two ports are allocated. * ata_pci_init_bmdma() exported to be used by LLDs in exotic cases. * port_info handling in all LLDs are standardized - all port_info arrays are const stack variable named ppi. Unless the second port is different from the first, its port_info is specified as NULL (tells libata that it's identical to the last non-NULL port_info). * pata_hpt37x/hpt3x2n: don't modify static variable directly. Make an on-stack copy instead as ata_piix does. * pata_uli: It has 4 ports instead of 2. Don't use ata_pci_prepare_native_host(). Allocate the host explicitly and use init helpers. It's simple enough. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
515 lines
12 KiB
C
515 lines
12 KiB
C
/*
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* pata_cmd64x.c - CMD64x PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Based upon
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* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
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*
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* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
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* Note, this driver is not used at all on other systems because
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* there the "BIOS" has done all of the following already.
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* Due to massive hardware bugs, UltraDMA is only supported
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* on the 646U2 and not on the 646U.
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*
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1998 David S. Miller (davem@redhat.com)
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*
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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*
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* TODO
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* Testing work
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_cmd64x"
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#define DRV_VERSION "0.2.2"
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/*
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* CMD64x specific registers definition.
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*/
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enum {
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CFR = 0x50,
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CFR_INTR_CH0 = 0x02,
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CNTRL = 0x51,
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CNTRL_DIS_RA0 = 0x40,
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CNTRL_DIS_RA1 = 0x80,
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CNTRL_ENA_2ND = 0x08,
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CMDTIM = 0x52,
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ARTTIM0 = 0x53,
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DRWTIM0 = 0x54,
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ARTTIM1 = 0x55,
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DRWTIM1 = 0x56,
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ARTTIM23 = 0x57,
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ARTTIM23_DIS_RA2 = 0x04,
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ARTTIM23_DIS_RA3 = 0x08,
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ARTTIM23_INTR_CH1 = 0x10,
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ARTTIM2 = 0x57,
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ARTTIM3 = 0x57,
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DRWTIM23 = 0x58,
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DRWTIM2 = 0x58,
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BRST = 0x59,
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DRWTIM3 = 0x5b,
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BMIDECR0 = 0x70,
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MRDMODE = 0x71,
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MRDMODE_INTR_CH0 = 0x04,
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MRDMODE_INTR_CH1 = 0x08,
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MRDMODE_BLK_CH0 = 0x10,
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MRDMODE_BLK_CH1 = 0x20,
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BMIDESR0 = 0x72,
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UDIDETCR0 = 0x73,
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DTPR0 = 0x74,
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BMIDECR1 = 0x78,
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BMIDECSR = 0x79,
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BMIDESR1 = 0x7A,
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UDIDETCR1 = 0x7B,
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DTPR1 = 0x7C
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};
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static int cmd648_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 r;
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/* Check cable detect bits */
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pci_read_config_byte(pdev, BMIDECSR, &r);
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if (r & (1 << ap->port_no))
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return ATA_CBL_PATA80;
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return ATA_CBL_PATA40;
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}
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/**
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* cmd64x_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup.
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*/
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static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct ata_timing t;
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const unsigned long T = 1000000 / 33;
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const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
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u8 reg;
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/* Port layout is not logical so use a table */
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const u8 arttim_port[2][2] = {
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{ ARTTIM0, ARTTIM1 },
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{ ARTTIM23, ARTTIM23 }
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};
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const u8 drwtim_port[2][2] = {
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{ DRWTIM0, DRWTIM1 },
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{ DRWTIM2, DRWTIM3 }
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};
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int arttim = arttim_port[ap->port_no][adev->devno];
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int drwtim = drwtim_port[ap->port_no][adev->devno];
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if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
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printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
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return;
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}
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if (ap->port_no) {
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/* Slave has shared address setup */
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struct ata_device *pair = ata_dev_pair(adev);
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if (pair) {
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struct ata_timing tp;
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ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
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ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
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}
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}
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printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
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t.active, t.recover, t.setup);
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if (t.recover > 16) {
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t.active += t.recover - 16;
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t.recover = 16;
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}
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if (t.active > 16)
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t.active = 16;
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/* Now convert the clocks into values we can actually stuff into
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the chip */
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if (t.recover > 1)
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t.recover--;
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else
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t.recover = 15;
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if (t.setup > 4)
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t.setup = 0xC0;
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else
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t.setup = setup_data[t.setup];
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t.active &= 0x0F; /* 0 = 16 */
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/* Load setup timing */
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pci_read_config_byte(pdev, arttim, ®);
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reg &= 0x3F;
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reg |= t.setup;
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pci_write_config_byte(pdev, arttim, reg);
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/* Load active/recovery */
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pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
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}
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/**
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* cmd64x_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the DMA mode setup.
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*/
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static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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static const u8 udma_data[] = {
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0x30, 0x20, 0x10, 0x20, 0x10, 0x00
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};
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static const u8 mwdma_data[] = {
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0x30, 0x20, 0x10
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 regU, regD;
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int pciU = UDIDETCR0 + 8 * ap->port_no;
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int pciD = BMIDESR0 + 8 * ap->port_no;
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int shift = 2 * adev->devno;
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pci_read_config_byte(pdev, pciD, ®D);
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pci_read_config_byte(pdev, pciU, ®U);
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/* DMA bits off */
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regD &= ~(0x20 << adev->devno);
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/* DMA control bits */
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regU &= ~(0x30 << shift);
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/* DMA timing bits */
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regU &= ~(0x05 << adev->devno);
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if (adev->dma_mode >= XFER_UDMA_0) {
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/* Merge thge timing value */
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regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
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/* Merge the control bits */
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regU |= 1 << adev->devno; /* UDMA on */
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if (adev->dma_mode > 2) /* 15nS timing */
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regU |= 4 << adev->devno;
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} else
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regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
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regD |= 0x20 << adev->devno;
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pci_write_config_byte(pdev, pciU, regU);
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pci_write_config_byte(pdev, pciD, regD);
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}
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/**
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* cmd648_dma_stop - DMA stop callback
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* @qc: Command in progress
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*
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* DMA has completed.
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*/
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static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 dma_intr;
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int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
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int dma_reg = ap->port_no ? ARTTIM2 : CFR;
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ata_bmdma_stop(qc);
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pci_read_config_byte(pdev, dma_reg, &dma_intr);
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pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
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}
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/**
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* cmd646r1_dma_stop - DMA stop callback
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* @qc: Command in progress
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*
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* Stub for now while investigating the r1 quirk in the old driver.
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*/
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static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
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{
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ata_bmdma_stop(qc);
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}
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static struct scsi_host_template cmd64x_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations cmd64x_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = cmd64x_set_piomode,
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.set_dmamode = cmd64x_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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static struct ata_port_operations cmd646r1_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = cmd64x_set_piomode,
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.set_dmamode = cmd64x_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = cmd646r1_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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static struct ata_port_operations cmd648_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = cmd64x_set_piomode,
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.set_dmamode = cmd64x_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = cmd648_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = cmd648_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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u32 class_rev;
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static const struct ata_port_info cmd_info[6] = {
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{ /* CMD 643 - no UDMA */
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.sht = &cmd64x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.port_ops = &cmd64x_port_ops
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},
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{ /* CMD 646 with broken UDMA */
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.sht = &cmd64x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.port_ops = &cmd64x_port_ops
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},
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{ /* CMD 646 with working UDMA */
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.sht = &cmd64x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA1,
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.port_ops = &cmd64x_port_ops
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},
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{ /* CMD 646 rev 1 */
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.sht = &cmd64x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.port_ops = &cmd646r1_port_ops
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},
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{ /* CMD 648 */
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.sht = &cmd64x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA2,
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.port_ops = &cmd648_port_ops
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},
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{ /* CMD 649 */
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.sht = &cmd64x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA3,
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.port_ops = &cmd648_port_ops
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}
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};
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const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
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u8 mrdmode;
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pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
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class_rev &= 0xFF;
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if (id->driver_data == 0) /* 643 */
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ata_pci_clear_simplex(pdev);
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if (pdev->device == PCI_DEVICE_ID_CMD_646) {
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/* Does UDMA work ? */
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if (class_rev > 4)
|
|
ppi[0] = &cmd_info[2];
|
|
/* Early rev with other problems ? */
|
|
else if (class_rev == 1)
|
|
ppi[0] = &cmd_info[3];
|
|
}
|
|
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
|
|
pci_read_config_byte(pdev, MRDMODE, &mrdmode);
|
|
mrdmode &= ~ 0x30; /* IRQ set up */
|
|
mrdmode |= 0x02; /* Memory read line enable */
|
|
pci_write_config_byte(pdev, MRDMODE, mrdmode);
|
|
|
|
/* Force PIO 0 here.. */
|
|
|
|
/* PPC specific fixup copied from old driver */
|
|
#ifdef CONFIG_PPC
|
|
pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
|
|
#endif
|
|
|
|
return ata_pci_init_one(pdev, ppi);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int cmd64x_reinit_one(struct pci_dev *pdev)
|
|
{
|
|
u8 mrdmode;
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
|
|
pci_read_config_byte(pdev, MRDMODE, &mrdmode);
|
|
mrdmode &= ~ 0x30; /* IRQ set up */
|
|
mrdmode |= 0x02; /* Memory read line enable */
|
|
pci_write_config_byte(pdev, MRDMODE, mrdmode);
|
|
#ifdef CONFIG_PPC
|
|
pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
|
|
#endif
|
|
return ata_pci_device_resume(pdev);
|
|
}
|
|
#endif
|
|
|
|
static const struct pci_device_id cmd64x[] = {
|
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
|
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
|
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
|
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
|
|
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver cmd64x_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = cmd64x,
|
|
.probe = cmd64x_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
#ifdef CONFIG_PM
|
|
.suspend = ata_pci_device_suspend,
|
|
.resume = cmd64x_reinit_one,
|
|
#endif
|
|
};
|
|
|
|
static int __init cmd64x_init(void)
|
|
{
|
|
return pci_register_driver(&cmd64x_pci_driver);
|
|
}
|
|
|
|
static void __exit cmd64x_exit(void)
|
|
{
|
|
pci_unregister_driver(&cmd64x_pci_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, cmd64x);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(cmd64x_init);
|
|
module_exit(cmd64x_exit);
|