44d0a87995
This patch adds ALSA SoC support for TI TLV320AIC3X audio codecs.
The features that are supported:
o Capture/Playback/Bypass.
o 16/20/24/32 bit audio.
o 8k - 96k sample rates.
o codec master only mode
o DAPM.
Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
182 lines
4.9 KiB
C
182 lines
4.9 KiB
C
/*
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* ALSA SoC TLV320AIC3X codec driver
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*
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* Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
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* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _AIC3X_H
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#define _AIC3X_H
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/* AIC3X register space */
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#define AIC3X_CACHEREGNUM 103
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/* Page select register */
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#define AIC3X_PAGE_SELECT 0
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/* Software reset register */
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#define AIC3X_RESET 1
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/* Codec Sample rate select register */
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#define AIC3X_SAMPLE_RATE_SEL_REG 2
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/* PLL progrramming register A */
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#define AIC3X_PLL_PROGA_REG 3
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/* PLL progrramming register B */
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#define AIC3X_PLL_PROGB_REG 4
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/* PLL progrramming register C */
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#define AIC3X_PLL_PROGC_REG 5
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/* PLL progrramming register D */
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#define AIC3X_PLL_PROGD_REG 6
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/* Codec datapath setup register */
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#define AIC3X_CODEC_DATAPATH_REG 7
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/* Audio serial data interface control register A */
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#define AIC3X_ASD_INTF_CTRLA 8
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/* Audio serial data interface control register B */
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#define AIC3X_ASD_INTF_CTRLB 9
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/* Audio overflow status and PLL R value programming register */
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#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
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/* ADC PGA Gain control registers */
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#define LADC_VOL 15
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#define RADC_VOL 16
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/* MIC3 control registers */
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#define MIC3LR_2_LADC_CTRL 17
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#define MIC3LR_2_RADC_CTRL 18
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/* Line1 Input control registers */
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#define LINE1L_2_LADC_CTRL 19
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#define LINE1R_2_RADC_CTRL 22
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/* Line2 Input control registers */
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#define LINE2L_2_LADC_CTRL 20
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#define LINE2R_2_RADC_CTRL 23
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/* MICBIAS Control Register */
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#define MICBIAS_CTRL 25
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/* AGC Control Registers A, B, C */
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#define LAGC_CTRL_A 26
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#define LAGC_CTRL_B 27
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#define LAGC_CTRL_C 28
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#define RAGC_CTRL_A 29
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#define RAGC_CTRL_B 30
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#define RAGC_CTRL_C 31
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/* DAC Power and Left High Power Output control registers */
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#define DAC_PWR 37
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#define HPLCOM_CFG 37
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/* Right High Power Output control registers */
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#define HPRCOM_CFG 38
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/* DAC Output Switching control registers */
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#define DAC_LINE_MUX 41
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/* High Power Output Driver Pop Reduction registers */
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#define HPOUT_POP_REDUCTION 42
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/* DAC Digital control registers */
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#define LDAC_VOL 43
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#define RDAC_VOL 44
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/* High Power Output control registers */
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#define LINE2L_2_HPLOUT_VOL 45
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#define LINE2R_2_HPROUT_VOL 62
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#define PGAL_2_HPLOUT_VOL 46
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#define PGAR_2_HPROUT_VOL 63
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#define DACL1_2_HPLOUT_VOL 47
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#define DACR1_2_HPROUT_VOL 64
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#define HPLOUT_CTRL 51
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#define HPROUT_CTRL 65
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/* High Power COM control registers */
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#define LINE2L_2_HPLCOM_VOL 52
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#define LINE2R_2_HPRCOM_VOL 69
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#define PGAL_2_HPLCOM_VOL 53
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#define PGAR_2_HPRCOM_VOL 70
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#define DACL1_2_HPLCOM_VOL 54
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#define DACR1_2_HPRCOM_VOL 71
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#define HPLCOM_CTRL 58
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#define HPRCOM_CTRL 72
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/* Mono Line Output Plus/Minus control registers */
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#define LINE2L_2_MONOLOPM_VOL 73
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#define LINE2R_2_MONOLOPM_VOL 76
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#define PGAL_2_MONOLOPM_VOL 74
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#define PGAR_2_MONOLOPM_VOL 77
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#define DACL1_2_MONOLOPM_VOL 75
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#define DACR1_2_MONOLOPM_VOL 78
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#define MONOLOPM_CTRL 79
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/* Line Output Plus/Minus control registers */
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#define LINE2L_2_LLOPM_VOL 80
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#define LINE2R_2_RLOPM_VOL 90
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#define PGAL_2_LLOPM_VOL 81
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#define PGAR_2_RLOPM_VOL 91
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#define DACL1_2_LLOPM_VOL 82
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#define DACR1_2_RLOPM_VOL 92
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#define LLOPM_CTRL 86
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#define RLOPM_CTRL 93
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/* Clock generation control register */
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#define AIC3X_CLKGEN_CTRL_REG 102
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/* Page select register bits */
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#define PAGE0_SELECT 0
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#define PAGE1_SELECT 1
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/* Audio serial data interface control register A bits */
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#define BIT_CLK_MASTER 0x80
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#define WORD_CLK_MASTER 0x40
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/* Codec Datapath setup register 7 */
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#define FSREF_44100 (1 << 7)
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#define FSREF_48000 (0 << 7)
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#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
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#define LDAC2LCH (0x1 << 3)
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#define RDAC2RCH (0x1 << 1)
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/* PLL registers bitfields */
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#define PLLP_SHIFT 0
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#define PLLR_SHIFT 0
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#define PLLJ_SHIFT 2
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#define PLLD_MSB_SHIFT 0
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#define PLLD_LSB_SHIFT 2
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/* Clock generation register bits */
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#define PLL_CLKIN_SHIFT 4
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#define MCLK_SOURCE 0x0
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#define PLL_CLKDIV_SHIFT 0
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/* Software reset register bits */
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#define SOFT_RESET 0x80
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/* PLL progrramming register A bits */
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#define PLL_ENABLE 0x80
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/* Route bits */
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#define ROUTE_ON 0x80
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/* Mute bits */
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#define UNMUTE 0x08
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#define MUTE_ON 0x80
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/* Power bits */
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#define LADC_PWR_ON 0x04
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#define RADC_PWR_ON 0x04
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#define LDAC_PWR_ON 0x80
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#define RDAC_PWR_ON 0x40
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#define HPLOUT_PWR_ON 0x01
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#define HPROUT_PWR_ON 0x01
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#define HPLCOM_PWR_ON 0x01
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#define HPRCOM_PWR_ON 0x01
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#define MONOLOPM_PWR_ON 0x01
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#define LLOPM_PWR_ON 0x01
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#define RLOPM_PWR_ON 0x01
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#define INVERT_VOL(val) (0x7f - val)
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/* Default output volume (inverted) */
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#define DEFAULT_VOL INVERT_VOL(0x50)
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/* Default input volume */
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#define DEFAULT_GAIN 0x20
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struct aic3x_setup_data {
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unsigned short i2c_address;
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};
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extern struct snd_soc_codec_dai aic3x_dai;
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extern struct snd_soc_codec_device soc_codec_dev_aic3x;
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#endif /* _AIC3X_H */
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