1b48cb563d
Fix 8bpp mode by adding handling of the Laguna chipsets to various places and stop trashing a HDR register which probably does not exist on the Laguna. Fix compilation warnings about uninitialized variables also. Finally, all 8bpp, 16bpp and 32bpp modes work on the Laguna chipset. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
123 lines
5.7 KiB
C
123 lines
5.7 KiB
C
/*
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* drivers/video/clgenfb.h - Cirrus Logic chipset constants
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*
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* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
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*
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* Original clgenfb author: Frank Neumann
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*
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* Based on retz3fb.c and clgen.c:
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* Copyright (C) 1997 Jes Sorensen
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* Copyright (C) 1996 Frank Neumann
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*
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***************************************************************
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*
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* Format this code with GNU indent '-kr -i8 -pcs' options.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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*/
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#ifndef __CLGENFB_H__
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#define __CLGENFB_H__
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/* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */
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/* OLD COMMENT: these definitions might most of the time also work */
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/* OLD COMMENT: for other CL-GD542x/543x based boards.. */
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/*** External/General Registers ***/
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#define CL_POS102 0x102 /* POS102 register */
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#define CL_VSSM 0x46e8 /* Adapter Sleep */
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#define CL_VSSM2 0x3c3 /* Motherboard Sleep */
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/*** VGA Sequencer Registers ***/
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/* the following are from the "extension registers" group */
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#define CL_SEQR6 0x6 /* Unlock ALL Extensions */
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#define CL_SEQR7 0x7 /* Extended Sequencer Mode */
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#define CL_SEQR8 0x8 /* EEPROM Control */
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#define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */
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#define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */
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#define CL_SEQRB 0xb /* VCLK0 Numerator */
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#define CL_SEQRC 0xc /* VCLK1 Numerator */
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#define CL_SEQRD 0xd /* VCLK2 Numerator */
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#define CL_SEQRE 0xe /* VCLK3 Numerator */
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#define CL_SEQRF 0xf /* DRAM Control */
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#define CL_SEQR10 0x10 /* Graphics Cursor X Position */
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#define CL_SEQR11 0x11 /* Graphics Cursor Y Position */
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#define CL_SEQR12 0x12 /* Graphics Cursor Attributes */
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#define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */
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#define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
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#define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
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#define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
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#define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */
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#define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */
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#define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */
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#define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */
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#define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */
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#define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */
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#define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */
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#define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */
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#define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */
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/*** CRT Controller Registers ***/
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#define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */
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#define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */
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#define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */
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/* the following are from the "extension registers" group */
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#define CL_CRT19 0x19 /* Interlace End */
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#define CL_CRT1A 0x1a /* Interlace Control */
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#define CL_CRT1B 0x1b /* Extended Display Controls */
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#define CL_CRT1C 0x1c /* Sync adjust and genlock register */
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#define CL_CRT1D 0x1d /* Overlay Extended Control register */
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#define CL_CRT1E 0x1e /* Another overflow register */
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#define CL_CRT25 0x25 /* Part Status Register */
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#define CL_CRT27 0x27 /* ID Register */
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#define CL_CRT51 0x51 /* P4 disable "flicker fixer" */
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/*** Graphics Controller Registers ***/
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/* the following are from the "extension registers" group */
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#define CL_GR9 0x9 /* Offset Register 0 */
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#define CL_GRA 0xa /* Offset Register 1 */
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#define CL_GRB 0xb /* Graphics Controller Mode Extensions */
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#define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */
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#define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */
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#define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */
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#define CL_GRF 0xf /* Display Compression Control register */
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#define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */
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#define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */
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#define CL_GR12 0x12 /* Background Color Byte 2 Register */
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#define CL_GR13 0x13 /* Foreground Color Byte 2 Register */
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#define CL_GR14 0x14 /* Background Color Byte 3 Register */
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#define CL_GR15 0x15 /* Foreground Color Byte 3 Register */
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/* the following are CL-GD5426/'28 specific blitter registers */
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#define CL_GR20 0x20 /* BLT Width Low */
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#define CL_GR21 0x21 /* BLT Width High */
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#define CL_GR22 0x22 /* BLT Height Low */
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#define CL_GR23 0x23 /* BLT Height High */
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#define CL_GR24 0x24 /* BLT Destination Pitch Low */
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#define CL_GR25 0x25 /* BLT Destination Pitch High */
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#define CL_GR26 0x26 /* BLT Source Pitch Low */
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#define CL_GR27 0x27 /* BLT Source Pitch High */
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#define CL_GR28 0x28 /* BLT Destination Start Low */
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#define CL_GR29 0x29 /* BLT Destination Start Mid */
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#define CL_GR2A 0x2a /* BLT Destination Start High */
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#define CL_GR2C 0x2c /* BLT Source Start Low */
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#define CL_GR2D 0x2d /* BLT Source Start Mid */
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#define CL_GR2E 0x2e /* BLT Source Start High */
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#define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */
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#define CL_GR30 0x30 /* BLT Mode */
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#define CL_GR31 0x31 /* BLT Start/Status */
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#define CL_GR32 0x32 /* BLT Raster Operation */
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#define CL_GR33 0x33 /* another P4 "compat" register.. */
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#define CL_GR34 0x34 /* Transparent Color Select Low */
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#define CL_GR35 0x35 /* Transparent Color Select High */
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#define CL_GR38 0x38 /* Source Transparent Color Mask Low */
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#define CL_GR39 0x39 /* Source Transparent Color Mask High */
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/*** Attribute Controller Registers ***/
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#define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */
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#define CL_AR34 0x34 /* TEST */
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#endif /* __CLGENFB_H__ */
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