d2212bc7db
Also, the us3_cpufreq driver can work on Ultra-IV and IV+. They use the SAFARI bus register to control the clock divider just like Ultra-III and III+ do. Signed-off-by: David S. Miller <davem@davemloft.net>
63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
/* $Id: head.h,v 1.30 1997/08/08 08:34:33 jj Exp $ */
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#ifndef _SPARC64_HEAD_H
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#define _SPARC64_HEAD_H
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#include <asm/pstate.h>
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#define KERNBASE 0x400000
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#define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
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#define __CHEETAH_ID 0x003e0014
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#define __JALAPENO_ID 0x003e0016
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#define CHEETAH_MANUF 0x003e
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#define CHEETAH_IMPL 0x0014 /* Ultra-III */
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#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
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#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
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#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
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#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
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#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
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#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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sethi %hi(__CHEETAH_ID), %tmp2; \
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srlx %tmp1, 32, %tmp1; \
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or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
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cmp %tmp1, %tmp2; \
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be,pn %icc, label; \
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nop;
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#define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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sethi %hi(__JALAPENO_ID), %tmp2; \
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srlx %tmp1, 32, %tmp1; \
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or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
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cmp %tmp1, %tmp2; \
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be,pn %icc, label; \
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nop;
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#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_MANUF; \
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bne,pt %xcc, 99f; \
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sllx %tmp1, 16, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_PLUS_IMPL; \
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bgeu,pt %xcc, label; \
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99: nop;
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#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_MANUF; \
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bne,pt %xcc, 99f; \
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sllx %tmp1, 16, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_IMPL; \
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bgeu,pt %xcc, label; \
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99: nop;
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#endif /* !(_SPARC64_HEAD_H) */
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