201 lines
5.2 KiB
C
201 lines
5.2 KiB
C
#ifndef _M68K_SYSTEM_H
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#define _M68K_SYSTEM_H
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/entry.h>
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#ifdef __KERNEL__
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/*
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* switch_to(n) should switch tasks to task ptr, first checking that
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* ptr isn't the current task, in which case it does nothing. This
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* also clears the TS-flag if the task we switched to has used the
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* math co-processor latest.
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*/
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/*
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* switch_to() saves the extra registers, that are not saved
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* automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
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* a0-a1. Some of these are used by schedule() and its predecessors
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* and so we might get see unexpected behaviors when a task returns
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* with unexpected register values.
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*
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* syscall stores these registers itself and none of them are used
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* by syscall after the function in the syscall has been called.
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*
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* Beware that resume now expects *next to be in d1 and the offset of
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* tss to be in a1. This saves a few instructions as we no longer have
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* to push them onto the stack and read them back right after.
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*
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* 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
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*
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* Changed 96/09/19 by Andreas Schwab
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* pass prev in a0, next in a1
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*/
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asmlinkage void resume(void);
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#define switch_to(prev,next,last) do { \
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register void *_prev __asm__ ("a0") = (prev); \
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register void *_next __asm__ ("a1") = (next); \
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register void *_last __asm__ ("d1"); \
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__asm__ __volatile__("jbsr resume" \
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: "=a" (_prev), "=a" (_next), "=d" (_last) \
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: "0" (_prev), "1" (_next) \
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: "d0", "d2", "d3", "d4", "d5"); \
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(last) = _last; \
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} while (0)
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/* interrupt control.. */
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#if 0
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#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
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#else
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#include <linux/hardirq.h>
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#define local_irq_enable() ({ \
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if (MACH_IS_Q40 || !hardirq_count()) \
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asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \
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})
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#endif
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#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
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#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
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#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
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static inline int irqs_disabled(void)
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{
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unsigned long flags;
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local_save_flags(flags);
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return flags & ~ALLOWINT;
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}
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/* For spinlocks etc */
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#define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); })
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/*
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* Force strict CPU ordering.
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* Not really required on m68k...
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*/
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#define nop() do { asm volatile ("nop"); barrier(); } while (0)
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((volatile struct __xchg_dummy *)(x))
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#ifndef CONFIG_RMW_INSNS
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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unsigned long flags, tmp;
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local_irq_save(flags);
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switch (size) {
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case 1:
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tmp = *(u8 *)ptr;
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*(u8 *)ptr = x;
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x = tmp;
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break;
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case 2:
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tmp = *(u16 *)ptr;
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*(u16 *)ptr = x;
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x = tmp;
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break;
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case 4:
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tmp = *(u32 *)ptr;
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*(u32 *)ptr = x;
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x = tmp;
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break;
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default:
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BUG();
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}
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local_irq_restore(flags);
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return x;
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}
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#else
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__
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("moveb %2,%0\n\t"
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"1:\n\t"
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"casb %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 2:
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__asm__ __volatile__
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("movew %2,%0\n\t"
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"1:\n\t"
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"casw %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 4:
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__asm__ __volatile__
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("movel %2,%0\n\t"
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"1:\n\t"
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"casl %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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}
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return x;
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}
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#endif
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#ifdef CONFIG_RMW_INSNS
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__ ("casb %0,%2,%1"
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: "=d" (old), "=m" (*(char *)p)
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: "d" (new), "0" (old), "m" (*(char *)p));
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break;
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case 2:
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__asm__ __volatile__ ("casw %0,%2,%1"
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: "=d" (old), "=m" (*(short *)p)
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: "d" (new), "0" (old), "m" (*(short *)p));
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break;
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case 4:
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__asm__ __volatile__ ("casl %0,%2,%1"
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: "=d" (old), "=m" (*(int *)p)
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: "d" (new), "0" (old), "m" (*(int *)p));
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break;
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}
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return old;
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}
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#endif
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif /* _M68K_SYSTEM_H */
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