cd378f18cf
Add support for IRQ migration across vector domain. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
164 lines
3.7 KiB
C
164 lines
3.7 KiB
C
/*
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* MSI hooks for standard x86 apic
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <asm/smp.h>
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/*
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* Shifts for APIC-based data
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*/
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#define MSI_DATA_VECTOR_SHIFT 0
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#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
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#define MSI_DATA_VECTOR_MASK 0xffffff00
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#define MSI_DATA_DELIVERY_SHIFT 8
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#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT)
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#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT)
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#define MSI_DATA_LEVEL_SHIFT 14
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#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
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#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
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#define MSI_DATA_TRIGGER_SHIFT 15
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#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
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#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
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/*
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* Shift/mask fields for APIC-based bus address
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*/
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#define MSI_TARGET_CPU_SHIFT 4
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#define MSI_ADDR_HEADER 0xfee00000
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#define MSI_ADDR_DESTID_MASK 0xfff0000f
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#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT)
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#define MSI_ADDR_DESTMODE_SHIFT 2
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#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
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#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
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#define MSI_ADDR_REDIRECTION_SHIFT 3
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#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
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#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
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static struct irq_chip ia64_msi_chip;
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#ifdef CONFIG_SMP
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static void ia64_set_msi_irq_affinity(unsigned int irq, cpumask_t cpu_mask)
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{
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struct msi_msg msg;
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u32 addr, data;
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int cpu = first_cpu(cpu_mask);
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if (!cpu_online(cpu))
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return;
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if (reassign_irq_vector(irq, cpu))
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return;
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read_msi_msg(irq, &msg);
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addr = msg.address_lo;
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addr &= MSI_ADDR_DESTID_MASK;
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addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(cpu));
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msg.address_lo = addr;
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data = msg.data;
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data &= MSI_DATA_VECTOR_MASK;
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data |= MSI_DATA_VECTOR(irq_to_vector(irq));
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msg.data = data;
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write_msi_msg(irq, &msg);
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irq_desc[irq].affinity = cpumask_of_cpu(cpu);
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}
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#endif /* CONFIG_SMP */
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int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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{
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struct msi_msg msg;
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unsigned long dest_phys_id;
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int irq, vector;
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cpumask_t mask;
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irq = create_irq();
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if (irq < 0)
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return irq;
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set_irq_msi(irq, desc);
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cpus_and(mask, irq_to_domain(irq), cpu_online_map);
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dest_phys_id = cpu_physical_id(first_cpu(mask));
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vector = irq_to_vector(irq);
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msg.address_hi = 0;
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msg.address_lo =
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MSI_ADDR_HEADER |
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MSI_ADDR_DESTMODE_PHYS |
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MSI_ADDR_REDIRECTION_CPU |
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MSI_ADDR_DESTID_CPU(dest_phys_id);
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msg.data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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MSI_DATA_DELIVERY_FIXED |
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MSI_DATA_VECTOR(vector);
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write_msi_msg(irq, &msg);
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set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
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return irq;
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}
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void ia64_teardown_msi_irq(unsigned int irq)
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{
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destroy_irq(irq);
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}
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static void ia64_ack_msi_irq(unsigned int irq)
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{
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move_native_irq(irq);
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ia64_eoi();
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}
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static int ia64_msi_retrigger_irq(unsigned int irq)
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{
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unsigned int vector = irq_to_vector(irq);
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ia64_resend_irq(vector);
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return 1;
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}
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/*
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* Generic ops used on most IA64 platforms.
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*/
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static struct irq_chip ia64_msi_chip = {
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.name = "PCI-MSI",
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.mask = mask_msi_irq,
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.unmask = unmask_msi_irq,
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.ack = ia64_ack_msi_irq,
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#ifdef CONFIG_SMP
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.set_affinity = ia64_set_msi_irq_affinity,
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#endif
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.retrigger = ia64_msi_retrigger_irq,
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};
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int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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{
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if (platform_setup_msi_irq)
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return platform_setup_msi_irq(pdev, desc);
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return ia64_setup_msi_irq(pdev, desc);
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}
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void arch_teardown_msi_irq(unsigned int irq)
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{
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if (platform_teardown_msi_irq)
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return platform_teardown_msi_irq(irq);
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return ia64_teardown_msi_irq(irq);
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}
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