b1c78c0fcc
- Convert CR* accesses to dedicated inline functions and rewrite the rest as C inlines - Don't do a double flush for global flushes (pointed out by Zach Amsden) This was a bug workaround for old CPUs that don't do 64bit and is obsolete. - Add a proper memory clobber to invlpg - Remove an unused extern Signed-off-by: Andi Kleen <ak@suse.de>
128 lines
3.1 KiB
C
128 lines
3.1 KiB
C
#ifndef _X8664_TLBFLUSH_H
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#define _X8664_TLBFLUSH_H
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#include <linux/mm.h>
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#include <asm/processor.h>
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static inline unsigned long get_cr3(void)
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{
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unsigned long cr3;
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asm volatile("mov %%cr3,%0" : "=r" (cr3));
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return cr3;
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}
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static inline void set_cr3(unsigned long cr3)
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{
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asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory");
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}
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static inline void __flush_tlb(void)
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{
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set_cr3(get_cr3());
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}
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static inline unsigned long get_cr4(void)
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{
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unsigned long cr4;
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asm volatile("mov %%cr4,%0" : "=r" (cr4));
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return cr4;
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}
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static inline void set_cr4(unsigned long cr4)
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{
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asm volatile("mov %0,%%cr4" :: "r" (cr4) : "memory");
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}
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static inline void __flush_tlb_all(void)
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{
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unsigned long cr4 = get_cr4();
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set_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */
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set_cr4(cr4); /* write old PGE again and flush TLBs */
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}
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#define __flush_tlb_one(addr) \
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__asm__ __volatile__("invlpg (%0)" :: "r" (addr) : "memory")
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/*
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* TLB flushing:
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*
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* - flush_tlb() flushes the current mm struct TLBs
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
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*
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* x86-64 can only flush individual pages or full VMs. For a range flush
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* we always do the full VM. Might be worth trying if for a small
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* range a few INVLPGs in a row are a win.
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*/
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#ifndef CONFIG_SMP
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#define flush_tlb() __flush_tlb()
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#define flush_tlb_all() __flush_tlb_all()
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#define local_flush_tlb() __flush_tlb()
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (mm == current->active_mm)
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__flush_tlb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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#else
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#include <asm/smp.h>
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#define local_flush_tlb() \
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__flush_tlb()
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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extern void flush_tlb_mm(struct mm_struct *);
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extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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#define flush_tlb() flush_tlb_current_task()
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static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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/* Roughly an IPI every 20MB with 4k pages for freeing page table
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ranges. Cost is about 42k of memory for each CPU. */
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#define ARCH_FREE_PTE_NR 5350
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#endif
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#define flush_tlb_kernel_range(start, end) flush_tlb_all()
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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/* x86_64 does not keep any page table caches in a software TLB.
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The CPUs do in their hardware TLBs, but they are handled
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by the normal TLB flushing algorithms. */
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}
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#endif /* _X8664_TLBFLUSH_H */
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