f9262c12c0
ATI chipsets tend to generate double timer interrupts for the local APIC timer when both the 8254 and the IO-APIC timer pins are enabled. This is because they route it to both and the result is anded together and the CPU ends up processing it twice. This patch changes check_timer to disable the 8254 routing for interrupt 0. I think it would be safe on all chipsets actually (i tested it on a couple and it worked everywhere) and Windows seems to do it in a similar way, but to be conservative this patch only enables this mode on ATI (and adds options to enable/disable too) Ported over from a similar x86-64 change. I reused the ACPI earlyquirk infrastructure for the ATI bridge check, but tweaked it a bit to work even without ACPI. Inspired by a patch from Chuck Ebbert, but redone. Cc: Chuck Ebbert <76306.1226@compuserve.com> Cc: "Brown, Len" <len.brown@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/config.h>
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#include <linux/pm.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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extern int enable_local_apic;
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extern int apic_verbosity;
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static inline void lapic_disable(void)
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{
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enable_local_apic = -1;
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clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
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}
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static inline void lapic_enable(void)
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{
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enable_local_apic = 1;
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}
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* Basic functions accessing APICs.
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*/
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static __inline void apic_write(unsigned long reg, unsigned long v)
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{
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*((volatile unsigned long *)(APIC_BASE+reg)) = v;
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}
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static __inline void apic_write_atomic(unsigned long reg, unsigned long v)
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{
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xchg((volatile unsigned long *)(APIC_BASE+reg), v);
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}
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static __inline unsigned long apic_read(unsigned long reg)
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{
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return *((volatile unsigned long *)(APIC_BASE+reg));
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}
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static __inline__ void apic_wait_icr_idle(void)
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{
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while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY )
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cpu_relax();
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}
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int get_physical_broadcast(void);
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x)
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# define apic_write_around(x,y) apic_write((x),(y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x,y) apic_write_atomic((x),(y))
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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extern void (*wait_timer_tick)(void);
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extern int get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC (void);
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extern void disconnect_bsp_APIC (int virt_wire_setup);
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extern void disable_local_APIC (void);
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extern void lapic_shutdown (void);
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extern int verify_local_APIC (void);
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extern void cache_APIC_registers (void);
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extern void sync_Arb_IDs (void);
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extern void init_bsp_APIC (void);
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extern void setup_local_APIC (void);
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extern void init_apic_mappings (void);
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extern void smp_local_timer_interrupt (struct pt_regs * regs);
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extern void setup_boot_APIC_clock (void);
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extern void setup_secondary_APIC_clock (void);
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extern void setup_apic_nmi_watchdog (void);
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extern int reserve_lapic_nmi(void);
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extern void release_lapic_nmi(void);
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extern void disable_timer_nmi_watchdog(void);
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extern void enable_timer_nmi_watchdog(void);
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extern void nmi_watchdog_tick (struct pt_regs * regs);
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extern int APIC_init_uniprocessor (void);
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extern void disable_APIC_timer(void);
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extern void enable_APIC_timer(void);
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extern void enable_NMI_through_LVT0 (void * dummy);
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extern unsigned int nmi_watchdog;
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#define NMI_NONE 0
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#define NMI_IO_APIC 1
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#define NMI_LOCAL_APIC 2
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#define NMI_INVALID 3
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extern int disable_timer_pin_1;
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void smp_send_timer_broadcast_ipi(struct pt_regs *regs);
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void switch_APIC_timer_to_ipi(void *cpumask);
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void switch_ipi_to_APIC_timer(void *cpumask);
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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extern int timer_over_8254;
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_APIC_H */
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