134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
/*
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* arch/mips/emma2rh/markeins/irq.c
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* This file defines the irq handler for EMMA2RH.
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*
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* Copyright (C) NEC Electronics Corporation 2004-2006
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*
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* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/delay.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/system.h>
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#include <asm/mipsregs.h>
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#include <asm/debug.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/emma2rh/emma2rh.h>
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/*
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* IRQ mapping
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*
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* 0-7: 8 CPU interrupts
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* 0 - software interrupt 0
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* 1 - software interrupt 1
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* 2 - most Vrc5477 interrupts are routed to this pin
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* 3 - (optional) some other interrupts routed to this pin for debugg
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* 4 - not used
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* 5 - not used
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* 6 - not used
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* 7 - cpu timer (used by default)
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*
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*/
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extern void emma2rh_sw_irq_init(u32 base);
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extern void emma2rh_gpio_irq_init(u32 base);
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extern void emma2rh_irq_init(u32 base);
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extern void emma2rh_irq_dispatch(void);
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static struct irqaction irq_cascade = {
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.handler = no_action,
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.flags = 0,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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.dev_id = NULL,
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.next = NULL,
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};
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void __init arch_init_irq(void)
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{
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u32 reg;
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db_run(printk("markeins_irq_setup invoked.\n"));
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/* by default, interrupts are disabled. */
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emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
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emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
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emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
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clear_c0_status(0xff00);
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set_c0_status(0x0400);
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#define GPIO_PCI (0xf<<15)
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/* setup GPIO interrupt for PCI interface */
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/* direction input */
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reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
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emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
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/* disable interrupt */
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
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emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
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/* level triggerd */
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
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emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
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reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
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emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
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/* interrupt clear */
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emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
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/* init all controllers */
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emma2rh_irq_init(EMMA2RH_IRQ_BASE);
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emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
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emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
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mips_cpu_irq_init(CPU_IRQ_BASE);
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/* setup cascade interrupts */
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setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
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setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
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setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause();
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if (pending & STATUSF_IP7)
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do_IRQ(CPU_IRQ_BASE + 7);
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else if (pending & STATUSF_IP2)
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emma2rh_irq_dispatch();
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else if (pending & STATUSF_IP1)
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do_IRQ(CPU_IRQ_BASE + 1);
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else if (pending & STATUSF_IP0)
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do_IRQ(CPU_IRQ_BASE + 0);
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else
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spurious_interrupt();
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}
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