51533b615e
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
296 lines
8.0 KiB
C
296 lines
8.0 KiB
C
#ifndef __gio_defs_h
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#define __gio_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/gio/rtl/gio_regs.r
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* id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
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* last modfied: Mon Apr 11 16:07:47 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
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* id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope gio */
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/* Register rw_pa_dout, scope gio, type rw */
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typedef struct {
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unsigned int data : 8;
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unsigned int dummy1 : 24;
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} reg_gio_rw_pa_dout;
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#define REG_RD_ADDR_gio_rw_pa_dout 0
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#define REG_WR_ADDR_gio_rw_pa_dout 0
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/* Register r_pa_din, scope gio, type r */
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typedef struct {
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unsigned int data : 8;
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unsigned int dummy1 : 24;
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} reg_gio_r_pa_din;
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#define REG_RD_ADDR_gio_r_pa_din 4
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/* Register rw_pa_oe, scope gio, type rw */
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typedef struct {
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unsigned int oe : 8;
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unsigned int dummy1 : 24;
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} reg_gio_rw_pa_oe;
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#define REG_RD_ADDR_gio_rw_pa_oe 8
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#define REG_WR_ADDR_gio_rw_pa_oe 8
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/* Register rw_intr_cfg, scope gio, type rw */
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typedef struct {
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unsigned int pa0 : 3;
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unsigned int pa1 : 3;
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unsigned int pa2 : 3;
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unsigned int pa3 : 3;
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unsigned int pa4 : 3;
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unsigned int pa5 : 3;
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unsigned int pa6 : 3;
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unsigned int pa7 : 3;
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unsigned int dummy1 : 8;
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} reg_gio_rw_intr_cfg;
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#define REG_RD_ADDR_gio_rw_intr_cfg 12
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#define REG_WR_ADDR_gio_rw_intr_cfg 12
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/* Register rw_intr_mask, scope gio, type rw */
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typedef struct {
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unsigned int pa0 : 1;
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unsigned int pa1 : 1;
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unsigned int pa2 : 1;
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unsigned int pa3 : 1;
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unsigned int pa4 : 1;
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unsigned int pa5 : 1;
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unsigned int pa6 : 1;
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unsigned int pa7 : 1;
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unsigned int dummy1 : 24;
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} reg_gio_rw_intr_mask;
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#define REG_RD_ADDR_gio_rw_intr_mask 16
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#define REG_WR_ADDR_gio_rw_intr_mask 16
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/* Register rw_ack_intr, scope gio, type rw */
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typedef struct {
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unsigned int pa0 : 1;
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unsigned int pa1 : 1;
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unsigned int pa2 : 1;
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unsigned int pa3 : 1;
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unsigned int pa4 : 1;
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unsigned int pa5 : 1;
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unsigned int pa6 : 1;
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unsigned int pa7 : 1;
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unsigned int dummy1 : 24;
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} reg_gio_rw_ack_intr;
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#define REG_RD_ADDR_gio_rw_ack_intr 20
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#define REG_WR_ADDR_gio_rw_ack_intr 20
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/* Register r_intr, scope gio, type r */
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typedef struct {
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unsigned int pa0 : 1;
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unsigned int pa1 : 1;
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unsigned int pa2 : 1;
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unsigned int pa3 : 1;
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unsigned int pa4 : 1;
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unsigned int pa5 : 1;
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unsigned int pa6 : 1;
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unsigned int pa7 : 1;
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unsigned int dummy1 : 24;
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} reg_gio_r_intr;
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#define REG_RD_ADDR_gio_r_intr 24
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/* Register r_masked_intr, scope gio, type r */
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typedef struct {
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unsigned int pa0 : 1;
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unsigned int pa1 : 1;
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unsigned int pa2 : 1;
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unsigned int pa3 : 1;
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unsigned int pa4 : 1;
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unsigned int pa5 : 1;
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unsigned int pa6 : 1;
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unsigned int pa7 : 1;
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unsigned int dummy1 : 24;
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} reg_gio_r_masked_intr;
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#define REG_RD_ADDR_gio_r_masked_intr 28
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/* Register rw_pb_dout, scope gio, type rw */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pb_dout;
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#define REG_RD_ADDR_gio_rw_pb_dout 32
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#define REG_WR_ADDR_gio_rw_pb_dout 32
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/* Register r_pb_din, scope gio, type r */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_r_pb_din;
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#define REG_RD_ADDR_gio_r_pb_din 36
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/* Register rw_pb_oe, scope gio, type rw */
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typedef struct {
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unsigned int oe : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pb_oe;
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#define REG_RD_ADDR_gio_rw_pb_oe 40
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#define REG_WR_ADDR_gio_rw_pb_oe 40
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/* Register rw_pc_dout, scope gio, type rw */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pc_dout;
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#define REG_RD_ADDR_gio_rw_pc_dout 48
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#define REG_WR_ADDR_gio_rw_pc_dout 48
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/* Register r_pc_din, scope gio, type r */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_r_pc_din;
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#define REG_RD_ADDR_gio_r_pc_din 52
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/* Register rw_pc_oe, scope gio, type rw */
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typedef struct {
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unsigned int oe : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pc_oe;
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#define REG_RD_ADDR_gio_rw_pc_oe 56
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#define REG_WR_ADDR_gio_rw_pc_oe 56
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/* Register rw_pd_dout, scope gio, type rw */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pd_dout;
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#define REG_RD_ADDR_gio_rw_pd_dout 64
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#define REG_WR_ADDR_gio_rw_pd_dout 64
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/* Register r_pd_din, scope gio, type r */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_r_pd_din;
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#define REG_RD_ADDR_gio_r_pd_din 68
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/* Register rw_pd_oe, scope gio, type rw */
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typedef struct {
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unsigned int oe : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pd_oe;
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#define REG_RD_ADDR_gio_rw_pd_oe 72
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#define REG_WR_ADDR_gio_rw_pd_oe 72
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/* Register rw_pe_dout, scope gio, type rw */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pe_dout;
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#define REG_RD_ADDR_gio_rw_pe_dout 80
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#define REG_WR_ADDR_gio_rw_pe_dout 80
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/* Register r_pe_din, scope gio, type r */
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typedef struct {
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unsigned int data : 18;
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unsigned int dummy1 : 14;
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} reg_gio_r_pe_din;
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#define REG_RD_ADDR_gio_r_pe_din 84
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/* Register rw_pe_oe, scope gio, type rw */
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typedef struct {
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unsigned int oe : 18;
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unsigned int dummy1 : 14;
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} reg_gio_rw_pe_oe;
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#define REG_RD_ADDR_gio_rw_pe_oe 88
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#define REG_WR_ADDR_gio_rw_pe_oe 88
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/* Constants */
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enum {
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regk_gio_anyedge = 0x00000007,
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regk_gio_hi = 0x00000001,
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regk_gio_lo = 0x00000002,
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regk_gio_negedge = 0x00000006,
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regk_gio_no = 0x00000000,
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regk_gio_off = 0x00000000,
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regk_gio_posedge = 0x00000005,
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regk_gio_rw_intr_cfg_default = 0x00000000,
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regk_gio_rw_intr_mask_default = 0x00000000,
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regk_gio_rw_pa_oe_default = 0x00000000,
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regk_gio_rw_pb_oe_default = 0x00000000,
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regk_gio_rw_pc_oe_default = 0x00000000,
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regk_gio_rw_pd_oe_default = 0x00000000,
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regk_gio_rw_pe_oe_default = 0x00000000,
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regk_gio_set = 0x00000003,
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regk_gio_yes = 0x00000001
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};
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#endif /* __gio_defs_h */
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