51533b615e
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
115 lines
3.7 KiB
C
115 lines
3.7 KiB
C
#ifndef __cris_defs_asm_h
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#define __cris_defs_asm_h
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/*
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* This file is autogenerated from
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* file: ../../inst/crisp/doc/cris.r
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* id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
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* last modfied: Mon Apr 11 16:06:39 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
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* id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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#ifndef REG_FIELD
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#define REG_FIELD( scope, reg, field, value ) \
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REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_FIELD_X_( value, shift ) ((value) << shift)
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#endif
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#ifndef REG_STATE
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#define REG_STATE( scope, reg, field, symbolic_value ) \
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REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_STATE_X_( k, shift ) (k << shift)
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#endif
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#ifndef REG_MASK
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#define REG_MASK( scope, reg, field ) \
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REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
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#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
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#endif
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#ifndef REG_LSB
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#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
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#endif
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#ifndef REG_BIT
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#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
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#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
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STRIDE_##scope##_##reg )
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#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
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((inst) + offs + (index) * stride)
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#endif
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/* Register rw_gc_cfg, scope cris, type rw */
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#define reg_cris_rw_gc_cfg___ic___lsb 0
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#define reg_cris_rw_gc_cfg___ic___width 1
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#define reg_cris_rw_gc_cfg___ic___bit 0
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#define reg_cris_rw_gc_cfg___dc___lsb 1
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#define reg_cris_rw_gc_cfg___dc___width 1
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#define reg_cris_rw_gc_cfg___dc___bit 1
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#define reg_cris_rw_gc_cfg___im___lsb 2
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#define reg_cris_rw_gc_cfg___im___width 1
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#define reg_cris_rw_gc_cfg___im___bit 2
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#define reg_cris_rw_gc_cfg___dm___lsb 3
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#define reg_cris_rw_gc_cfg___dm___width 1
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#define reg_cris_rw_gc_cfg___dm___bit 3
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#define reg_cris_rw_gc_cfg___gb___lsb 4
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#define reg_cris_rw_gc_cfg___gb___width 1
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#define reg_cris_rw_gc_cfg___gb___bit 4
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#define reg_cris_rw_gc_cfg___gk___lsb 5
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#define reg_cris_rw_gc_cfg___gk___width 1
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#define reg_cris_rw_gc_cfg___gk___bit 5
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#define reg_cris_rw_gc_cfg___gp___lsb 6
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#define reg_cris_rw_gc_cfg___gp___width 1
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#define reg_cris_rw_gc_cfg___gp___bit 6
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#define reg_cris_rw_gc_cfg_offset 0
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/* Register rw_gc_ccs, scope cris, type rw */
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#define reg_cris_rw_gc_ccs_offset 4
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/* Register rw_gc_srs, scope cris, type rw */
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#define reg_cris_rw_gc_srs___srs___lsb 0
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#define reg_cris_rw_gc_srs___srs___width 8
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#define reg_cris_rw_gc_srs_offset 8
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/* Register rw_gc_nrp, scope cris, type rw */
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#define reg_cris_rw_gc_nrp_offset 12
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/* Register rw_gc_exs, scope cris, type rw */
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#define reg_cris_rw_gc_exs_offset 16
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/* Register rw_gc_eda, scope cris, type rw */
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#define reg_cris_rw_gc_eda_offset 20
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/* Register rw_gc_r0, scope cris, type rw */
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#define reg_cris_rw_gc_r0_offset 32
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/* Register rw_gc_r1, scope cris, type rw */
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#define reg_cris_rw_gc_r1_offset 36
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/* Register rw_gc_r2, scope cris, type rw */
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#define reg_cris_rw_gc_r2_offset 40
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/* Register rw_gc_r3, scope cris, type rw */
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#define reg_cris_rw_gc_r3_offset 44
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/* Constants */
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#define regk_cris_no 0x00000000
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#define regk_cris_rw_gc_cfg_default 0x00000000
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#define regk_cris_yes 0x00000001
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#endif /* __cris_defs_asm_h */
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