36d57ac4a8
The size of auxiliary vector is fixed at 42 in linux/sched.h. But it isn't very obvious when looking at linux/elf.h. This patch adds AT_VECTOR_SIZE so that we can change it if necessary when a new vector is added. Because of include file ordering problems, doing this necessitated the extraction of the AT_* symbols into a standalone header file. Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
388 lines
16 KiB
C
388 lines
16 KiB
C
#ifndef __PPC64_ELF_H
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#define __PPC64_ELF_H
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#include <asm/cputable.h>
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#include <asm/auxvec.h>
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/* PowerPC relocations defined by the ABIs */
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#define R_PPC_NONE 0
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#define R_PPC_ADDR32 1 /* 32bit absolute address */
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#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
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#define R_PPC_ADDR16 3 /* 16bit absolute address */
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#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
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#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
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#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
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#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
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#define R_PPC_ADDR14_BRTAKEN 8
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#define R_PPC_ADDR14_BRNTAKEN 9
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#define R_PPC_REL24 10 /* PC relative 26 bit */
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#define R_PPC_REL14 11 /* PC relative 16 bit */
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#define R_PPC_REL14_BRTAKEN 12
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#define R_PPC_REL14_BRNTAKEN 13
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#define R_PPC_GOT16 14
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#define R_PPC_GOT16_LO 15
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#define R_PPC_GOT16_HI 16
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#define R_PPC_GOT16_HA 17
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#define R_PPC_PLTREL24 18
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#define R_PPC_COPY 19
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#define R_PPC_GLOB_DAT 20
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#define R_PPC_JMP_SLOT 21
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#define R_PPC_RELATIVE 22
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#define R_PPC_LOCAL24PC 23
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#define R_PPC_UADDR32 24
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#define R_PPC_UADDR16 25
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#define R_PPC_REL32 26
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#define R_PPC_PLT32 27
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#define R_PPC_PLTREL32 28
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#define R_PPC_PLT16_LO 29
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#define R_PPC_PLT16_HI 30
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#define R_PPC_PLT16_HA 31
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#define R_PPC_SDAREL16 32
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#define R_PPC_SECTOFF 33
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#define R_PPC_SECTOFF_LO 34
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#define R_PPC_SECTOFF_HI 35
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#define R_PPC_SECTOFF_HA 36
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/* PowerPC relocations defined for the TLS access ABI. */
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#define R_PPC_TLS 67 /* none (sym+add)@tls */
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#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
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#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
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#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
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#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
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#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
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#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
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#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
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#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
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#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
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#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
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#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
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#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
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#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
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#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
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#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
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#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
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#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
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#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
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#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
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#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
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#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
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#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
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#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
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#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
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#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
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#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
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#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
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/* Keep this the last entry. */
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#define R_PPC_NUM 95
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/*
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* ELF register definitions..
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/ptrace.h>
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#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
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#define ELF_NFPREG 33 /* includes fpscr */
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#define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
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#define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
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typedef unsigned long elf_greg_t64;
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typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
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typedef unsigned int elf_greg_t32;
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typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
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/*
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* These are used to set parameters in the core dumps.
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*/
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#ifndef ELF_ARCH
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# define ELF_ARCH EM_PPC64
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# define ELF_CLASS ELFCLASS64
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# define ELF_DATA ELFDATA2MSB
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typedef elf_greg_t64 elf_greg_t;
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typedef elf_gregset_t64 elf_gregset_t;
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# define elf_addr_t unsigned long
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#else
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/* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
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typedef elf_greg_t32 elf_greg_t;
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typedef elf_gregset_t32 elf_gregset_t;
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# define elf_addr_t u32
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#endif
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typedef double elf_fpreg_t;
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typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
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/* Altivec registers */
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/*
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* The entries with indexes 0-31 contain the corresponding vector registers.
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* The entry with index 32 contains the vscr as the last word (offset 12)
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* within the quadword. This allows the vscr to be stored as either a
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* quadword (since it must be copied via a vector register to/from storage)
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* or as a word. The entry with index 33 contains the vrsave as the first
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* word (offset 0) within the quadword.
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*
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* This definition of the VMX state is compatible with the current PPC32
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* ptrace interface. This allows signal handling and ptrace to use the same
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* structures. This also simplifies the implementation of a bi-arch
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* (combined (32- and 64-bit) gdb.
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*
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* Note that it's _not_ compatible with 32 bits ucontext which stuffs the
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* vrsave along with vscr and so only uses 33 vectors for the register set
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*/
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typedef __vector128 elf_vrreg_t;
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typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
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typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
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/*
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* This is used to ensure we don't load something for the wrong architecture.
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*/
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#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
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#define USE_ELF_CORE_DUMP
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#define ELF_EXEC_PAGESIZE 4096
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/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
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use of this is to invoke "./ld.so someprog" to test out a new version of
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the loader. We need to make sure that it is out of the way of the program
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that it will "exec", and that there is sufficient room for the brk. */
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#define ELF_ET_DYN_BASE (0x08000000)
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#ifdef __KERNEL__
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/* Common routine for both 32-bit and 64-bit processes */
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static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs,
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struct pt_regs *regs)
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{
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int i;
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int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64);
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if (gprs > ELF_NGREG)
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gprs = ELF_NGREG;
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for (i=0; i < gprs; i++)
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elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i];
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}
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#define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs);
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static inline int dump_task_regs(struct task_struct *tsk,
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elf_gregset_t *elf_regs)
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{
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struct pt_regs *regs = tsk->thread.regs;
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if (regs)
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ppc64_elf_core_copy_regs(*elf_regs, regs);
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return 1;
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}
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#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
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extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
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#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
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/* XXX Should we define the XFPREGS using altivec ??? */
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#endif
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/* This yields a mask that user programs can use to figure out what
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instruction set this cpu supports. This could be done in userspace,
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but it's not easy, and we've already done it here. */
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#define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
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/* This yields a string that ld.so will use to load implementation
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specific libraries for optimization. This is more specific in
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intent than poking at uname or /proc/cpuinfo.
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For the moment, we have only optimizations for the Intel generations,
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but that could change... */
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#define ELF_PLATFORM (NULL)
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#define ELF_PLAT_INIT(_r, load_addr) do { \
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memset(_r->gpr, 0, sizeof(_r->gpr)); \
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_r->ctr = _r->link = _r->xer = _r->ccr = 0; \
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_r->gpr[2] = load_addr; \
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} while (0)
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#ifdef __KERNEL__
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#define SET_PERSONALITY(ex, ibcs2) \
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do { \
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unsigned long new_flags = 0; \
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if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
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new_flags = _TIF_32BIT; \
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if ((current_thread_info()->flags & _TIF_32BIT) \
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!= new_flags) \
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set_thread_flag(TIF_ABI_PENDING); \
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else \
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clear_thread_flag(TIF_ABI_PENDING); \
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if (personality(current->personality) != PER_LINUX32) \
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set_personality(PER_LINUX); \
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} while (0)
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/*
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* An executable for which elf_read_implies_exec() returns TRUE will
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* have the READ_IMPLIES_EXEC personality flag set automatically. This
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* is only required to work around bugs in old 32bit toolchains. Since
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* the 64bit ABI has never had these issues dont enable the workaround
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* even if we have an executable stack.
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*/
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#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
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(exec_stk != EXSTACK_DISABLE_X) : 0)
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#endif
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extern int dcache_bsize;
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extern int icache_bsize;
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extern int ucache_bsize;
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/* We do have an arch_setup_additional_pages for vDSO matters */
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#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
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struct linux_binprm;
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extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
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/*
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* The requirements here are:
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* - keep the final alignment of sp (sp & 0xf)
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* - make sure the 32-bit value at the first 16 byte aligned position of
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* AUXV is greater than 16 for glibc compatibility.
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* AT_IGNOREPPC is used for that.
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* - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
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* even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
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*/
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#define ARCH_DLINFO \
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do { \
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/* Handle glibc compatibility. */ \
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NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
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NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
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/* Cache size items */ \
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NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
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NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
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NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
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/* vDSO base */ \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base); \
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} while (0)
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/* PowerPC64 relocations defined by the ABIs */
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#define R_PPC64_NONE R_PPC_NONE
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#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
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#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
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#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
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#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
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#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
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#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
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#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
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#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
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#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
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#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
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#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
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#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
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#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
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#define R_PPC64_GOT16 R_PPC_GOT16
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#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
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#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
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#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
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#define R_PPC64_COPY R_PPC_COPY
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#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
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#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
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#define R_PPC64_RELATIVE R_PPC_RELATIVE
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#define R_PPC64_UADDR32 R_PPC_UADDR32
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#define R_PPC64_UADDR16 R_PPC_UADDR16
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#define R_PPC64_REL32 R_PPC_REL32
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#define R_PPC64_PLT32 R_PPC_PLT32
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#define R_PPC64_PLTREL32 R_PPC_PLTREL32
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#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
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#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
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#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
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#define R_PPC64_SECTOFF R_PPC_SECTOFF
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#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
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#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
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#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
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#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
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#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
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#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
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#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
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#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
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#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
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#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
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#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
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#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
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#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
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#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
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#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
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#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
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#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
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#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
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#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
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#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
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#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
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#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
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#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
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#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
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#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
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#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
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#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
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#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
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#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
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#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
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#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
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#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
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#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
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/* PowerPC64 relocations defined for the TLS access ABI. */
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#define R_PPC64_TLS 67 /* none (sym+add)@tls */
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#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
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#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
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#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
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#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
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#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
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#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
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#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
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#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
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#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
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#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
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#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
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#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
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#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
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#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
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#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
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#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
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#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
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#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
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#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
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#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
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#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
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#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
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#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
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#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
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#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
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#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
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#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
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#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
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#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
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#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
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#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
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#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
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#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
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#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
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#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
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#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
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#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
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#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
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#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
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/* Keep this the last entry. */
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#define R_PPC64_NUM 107
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#endif /* __PPC64_ELF_H */
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