2ba71978c0
This patch cleans last ac97 audio/modem codec interception in initialization procedures (ac97_mixer_new()) and removes obsolete SHARED_TYPE 'locking' which prevents from AMC codecs to function correctly. Signed-off-by: Sasha Khapyorsky <sashak@smlink.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
604 lines
26 KiB
C
604 lines
26 KiB
C
#ifndef __SOUND_AC97_CODEC_H
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#define __SOUND_AC97_CODEC_H
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/*
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* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
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* Universal interface for Audio Codec '97
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*
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* For more details look to AC '97 component specification revision 2.1
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* by Intel Corporation (http://developer.intel.com).
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include "pcm.h"
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#include "control.h"
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#include "info.h"
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/*
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* AC'97 codec registers
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*/
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#define AC97_RESET 0x00 /* Reset */
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#define AC97_MASTER 0x02 /* Master Volume */
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#define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
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#define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
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#define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
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#define AC97_PC_BEEP 0x0a /* PC Beep Volume (optinal) */
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#define AC97_PHONE 0x0c /* Phone Volume (optional) */
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#define AC97_MIC 0x0e /* MIC Volume */
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#define AC97_LINE 0x10 /* Line In Volume */
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#define AC97_CD 0x12 /* CD Volume */
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#define AC97_VIDEO 0x14 /* Video Volume (optional) */
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#define AC97_AUX 0x16 /* AUX Volume (optional) */
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#define AC97_PCM 0x18 /* PCM Volume */
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#define AC97_REC_SEL 0x1a /* Record Select */
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#define AC97_REC_GAIN 0x1c /* Record Gain */
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#define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */
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#define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */
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#define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */
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#define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */
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#define AC97_POWERDOWN 0x26 /* Powerdown control / status */
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/* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
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#define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */
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#define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */
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#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
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#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
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#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
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#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
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#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
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#define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */
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#define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */
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#define AC97_SPDIF 0x3a /* S/PDIF control */
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/* range 0x3c-0x58 - MODEM */
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#define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */
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#define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */
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#define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */
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#define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */
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#define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */
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#define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */
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#define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */
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#define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */
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#define AC97_GPIO_CFG 0x4c /* GPIO Configuration */
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#define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */
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#define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */
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#define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */
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#define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */
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#define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */
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/* range 0x5a-0x7b - Vendor Specific */
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#define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */
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#define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */
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/* range 0x60-0x6f (page 1) - extended codec registers */
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#define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */
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#define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */
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#define AC97_PCI_SID 0x64 /* PCI Subsystem ID */
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#define AC97_FUNC_SELECT 0x66 /* Function Select */
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#define AC97_FUNC_INFO 0x68 /* Function Information */
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#define AC97_SENSE_INFO 0x6a /* Sense Details */
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/* slot allocation */
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#define AC97_SLOT_TAG 0
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#define AC97_SLOT_CMD_ADDR 1
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#define AC97_SLOT_CMD_DATA 2
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#define AC97_SLOT_PCM_LEFT 3
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#define AC97_SLOT_PCM_RIGHT 4
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#define AC97_SLOT_MODEM_LINE1 5
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#define AC97_SLOT_PCM_CENTER 6
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#define AC97_SLOT_MIC 6 /* input */
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#define AC97_SLOT_SPDIF_LEFT1 6
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#define AC97_SLOT_PCM_SLEFT 7 /* surround left */
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#define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */
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#define AC97_SLOT_SPDIF_LEFT 7
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#define AC97_SLOT_PCM_SRIGHT 8 /* surround right */
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#define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */
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#define AC97_SLOT_SPDIF_RIGHT 8
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#define AC97_SLOT_LFE 9
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#define AC97_SLOT_SPDIF_RIGHT1 9
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#define AC97_SLOT_MODEM_LINE2 10
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#define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */
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#define AC97_SLOT_SPDIF_LEFT2 10
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#define AC97_SLOT_HANDSET 11 /* output */
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#define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */
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#define AC97_SLOT_SPDIF_RIGHT2 11
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#define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */
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#define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */
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/* basic capabilities (reset register) */
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#define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */
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#define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */
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#define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */
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#define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */
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#define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */
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#define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */
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#define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
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#define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
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#define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
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#define AC97_BC_DAC_MASK 0x00c0
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#define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
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#define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
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#define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */
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#define AC97_BC_ADC_MASK 0x0300
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/* general purpose */
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#define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */
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#define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */
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#define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */
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/* extended audio ID bit defines */
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#define AC97_EI_VRA 0x0001 /* Variable bit rate supported */
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#define AC97_EI_DRA 0x0002 /* Double rate supported */
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#define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */
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#define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */
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#define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */
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#define AC97_EI_DACS_SLOT_SHIFT 4
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#define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */
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#define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */
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#define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */
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#define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */
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#define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */
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#define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */
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#define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */
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#define AC97_EI_REV_SHIFT 10
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#define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */
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#define AC97_EI_ADDR_SHIFT 14
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/* extended audio status and control bit defines */
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#define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */
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#define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */
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#define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */
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#define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */
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#define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */
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#define AC97_EA_SPSA_SLOT_SHIFT 4
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#define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */
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#define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */
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#define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */
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#define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */
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#define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */
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#define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */
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#define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */
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#define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */
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#define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */
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#define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */
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#define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */
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#define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */
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#define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */
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/* S/PDIF control bit defines */
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#define AC97_SC_PRO 0x0001 /* Professional status */
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#define AC97_SC_NAUDIO 0x0002 /* Non audio stream */
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#define AC97_SC_COPY 0x0004 /* Copyright status */
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#define AC97_SC_PRE 0x0008 /* Preemphasis status */
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#define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */
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#define AC97_SC_CC_SHIFT 4
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#define AC97_SC_L 0x0800 /* Generation Level status */
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#define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */
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#define AC97_SC_SPSR_SHIFT 12
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#define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
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#define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */
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#define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */
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#define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */
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#define AC97_SC_V 0x8000 /* Validity status */
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/* Interrupt and Paging bit defines (AC'97 2.3) */
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#define AC97_PAGE_MASK 0x000f /* Page Selector */
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#define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */
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#define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */
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#define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */
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#define AC97_INT_SENSE 0x1000 /* Sense Cycle */
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#define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */
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#define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */
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#define AC97_INT_STATUS 0x8000 /* Interrupt Status */
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/* extended modem ID bit defines */
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#define AC97_MEI_LINE1 0x0001 /* Line1 present */
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#define AC97_MEI_LINE2 0x0002 /* Line2 present */
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#define AC97_MEI_HANDSET 0x0004 /* Handset present */
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#define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */
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#define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */
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#define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */
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#define AC97_MEI_ADDR_SHIFT 14
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/* extended modem status and control bit defines */
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#define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */
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#define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */
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#define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */
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#define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */
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#define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */
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#define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */
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#define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */
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#define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */
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#define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */
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#define AC97_MEA_PRB 0x0200 /* reserved */
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#define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */
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#define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */
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#define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */
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#define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */
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#define AC97_MEA_PRG 0x4000 /* HADC power down (high) */
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#define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */
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/* modem gpio status defines */
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#define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */
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#define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */
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#define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */
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#define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */
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#define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */
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#define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */
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#define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */
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#define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */
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#define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */
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#define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */
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#define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */
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#define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */
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#define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */
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#define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */
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#define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */
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#define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */
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/* specific - SigmaTel */
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#define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */
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#define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */
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#define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */
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#define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
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#define AC97_SIGMATEL_DAC2INVERT 0x6e
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#define AC97_SIGMATEL_BIAS1 0x70
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#define AC97_SIGMATEL_BIAS2 0x72
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#define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */
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#define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
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#define AC97_SIGMATEL_CIC1 0x76
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#define AC97_SIGMATEL_CIC2 0x78
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/* specific - Analog Devices */
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#define AC97_AD_TEST 0x5a /* test register */
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#define AC97_AD_CODEC_CFG 0x70 /* codec configuration */
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#define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */
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#define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */
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#define AC97_AD_MISC 0x76 /* Misc Control Bits */
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/* specific - Cirrus Logic */
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#define AC97_CSR_ACMODE 0x5e /* AC Mode Register */
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#define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */
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#define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */
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#define AC97_CSR_SERIAL 0x6a /* Serial Port Control */
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#define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */
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#define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */
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#define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */
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/* specific - Conexant */
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#define AC97_CXR_AUDIO_MISC 0x5c
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#define AC97_CXR_SPDIFEN (1<<3)
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#define AC97_CXR_COPYRGT (1<<2)
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#define AC97_CXR_SPDIF_MASK (3<<0)
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#define AC97_CXR_SPDIF_PCM 0x0
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#define AC97_CXR_SPDIF_AC3 0x2
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/* specific - ALC */
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#define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60
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/* S/PDIF input status 1 bit defines */
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#define AC97_ALC650_PRO 0x0001 /* Professional status */
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#define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */
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#define AC97_ALC650_COPY 0x0004 /* Copyright status */
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#define AC97_ALC650_PRE 0x0038 /* Preemphasis status */
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#define AC97_ALC650_PRE_SHIFT 3
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#define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */
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#define AC97_ALC650_MODE_SHIFT 6
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#define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */
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#define AC97_ALC650_CC_SHIFT 8
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#define AC97_ALC650_L 0x8000 /* Generation Level status */
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#define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62
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/* S/PDIF input status 2 bit defines */
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#define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */
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#define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
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#define AC97_ALC650_CHANNEL_SHIFT 4
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#define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */
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#define AC97_ALC650_SPSR_SHIFT 8
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#define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
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#define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */
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#define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */
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#define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */
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#define AC97_ALC650_CLOCK_SHIFT 12
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#define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */
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#define AC97_ALC650_V 0x8000 /* Validity status */
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#define AC97_ALC650_SURR_DAC_VOL 0x64
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#define AC97_ALC650_LFE_DAC_VOL 0x66
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#define AC97_ALC650_UNKNOWN1 0x68
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#define AC97_ALC650_MULTICH 0x6a
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#define AC97_ALC650_UNKNOWN2 0x6c
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#define AC97_ALC650_REVISION 0x6e
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#define AC97_ALC650_UNKNOWN3 0x70
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#define AC97_ALC650_UNKNOWN4 0x72
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#define AC97_ALC650_MISC 0x74
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#define AC97_ALC650_GPIO_SETUP 0x76
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#define AC97_ALC650_GPIO_STATUS 0x78
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#define AC97_ALC650_CLOCK 0x7a
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/* specific - Yamaha YMF753 */
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#define AC97_YMF753_DIT_CTRL2 0x66 /* DIT Control 2 */
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#define AC97_YMF753_3D_MODE_SEL 0x68 /* 3D Mode Select */
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/* specific - C-Media */
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#define AC97_CM9738_VENDOR_CTRL 0x5a
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#define AC97_CM9739_MULTI_CHAN 0x64
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#define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */
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#define AC97_CM9739_SPDIF_CTRL 0x6c
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/* specific - wolfson */
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#define AC97_WM97XX_FMIXER_VOL 0x72
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#define AC97_WM9704_RMIXER_VOL 0x74
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#define AC97_WM9704_TEST 0x5a
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#define AC97_WM9704_RPCM_VOL 0x70
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#define AC97_WM9711_OUT3VOL 0x16
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/* ac97->scaps */
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#define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */
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#define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */
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#define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */
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#define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */
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#define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */
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#define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */
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#define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */
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#define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */
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#define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */
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#define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */
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/* ac97->flags */
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#define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */
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#define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */
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#define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */
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#define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */
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#define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */
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#define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */
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#define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */
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#define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */
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#define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */
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#define AC97_MODEM_PATCH (1<<9) /* modem patch */
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#define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */
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#define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */
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#define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */
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#define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */
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#define AC97_HAS_NO_CD (1<<14) /* no CD volume */
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#define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */
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#define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */
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#define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */
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/* rates indexes */
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#define AC97_RATES_FRONT_DAC 0
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#define AC97_RATES_SURR_DAC 1
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#define AC97_RATES_LFE_DAC 2
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#define AC97_RATES_ADC 3
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#define AC97_RATES_MIC_ADC 4
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#define AC97_RATES_SPDIF 5
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/*
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*
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*/
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typedef struct _snd_ac97_bus ac97_bus_t;
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typedef struct _snd_ac97_bus_ops ac97_bus_ops_t;
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typedef struct _snd_ac97_template ac97_template_t;
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typedef struct _snd_ac97 ac97_t;
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enum ac97_pcm_cfg {
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AC97_PCM_CFG_FRONT = 2,
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AC97_PCM_CFG_REAR = 10, /* alias surround */
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AC97_PCM_CFG_LFE = 11, /* center + lfe */
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AC97_PCM_CFG_40 = 4, /* front + rear */
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AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */
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AC97_PCM_CFG_SPDIF = 20
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};
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/* PCM allocation */
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struct ac97_pcm {
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ac97_bus_t *bus;
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unsigned int stream: 1, /* stream type: 1 = capture */
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exclusive: 1, /* exclusive mode, don't override with other pcms */
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copy_flag: 1, /* lowlevel driver must fill all entries */
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spdif: 1; /* spdif pcm */
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unsigned short aslots; /* active slots */
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unsigned int rates; /* available rates */
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struct {
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unsigned short slots; /* driver input: requested AC97 slot numbers */
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unsigned short rslots[4]; /* allocated slots per codecs */
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unsigned char rate_table[4];
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ac97_t *codec[4]; /* allocated codecs */
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} r[2]; /* 0 = standard rates, 1 = double rates */
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unsigned long private_value; /* used by the hardware driver */
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};
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struct snd_ac97_build_ops {
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int (*build_3d) (ac97_t *ac97);
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int (*build_specific) (ac97_t *ac97);
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int (*build_spdif) (ac97_t *ac97);
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int (*build_post_spdif) (ac97_t *ac97);
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#ifdef CONFIG_PM
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void (*suspend) (ac97_t *ac97);
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void (*resume) (ac97_t *ac97);
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#endif
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void (*update_jacks) (ac97_t *ac97); /* for jack-sharing */
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};
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struct _snd_ac97_bus_ops {
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void (*reset) (ac97_t *ac97);
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void (*write) (ac97_t *ac97, unsigned short reg, unsigned short val);
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unsigned short (*read) (ac97_t *ac97, unsigned short reg);
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void (*wait) (ac97_t *ac97);
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void (*init) (ac97_t *ac97);
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};
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struct _snd_ac97_bus {
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/* -- lowlevel (hardware) driver specific -- */
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ac97_bus_ops_t *ops;
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void *private_data;
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void (*private_free) (ac97_bus_t *bus);
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/* --- */
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snd_card_t *card;
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unsigned short num; /* bus number */
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unsigned short no_vra: 1, /* bridge doesn't support VRA */
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dra: 1, /* bridge supports double rate */
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isdin: 1;/* independent SDIN */
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unsigned int clock; /* AC'97 base clock (usually 48000Hz) */
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spinlock_t bus_lock; /* used mainly for slot allocation */
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unsigned short used_slots[2][4]; /* actually used PCM slots */
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unsigned short pcms_count; /* count of PCMs */
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struct ac97_pcm *pcms;
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ac97_t *codec[4];
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snd_info_entry_t *proc;
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};
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struct _snd_ac97_template {
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void *private_data;
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void (*private_free) (ac97_t *ac97);
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struct pci_dev *pci; /* assigned PCI device - used for quirks */
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unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
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unsigned short addr; /* physical address of codec [0-3] */
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|
unsigned int scaps; /* driver capabilities */
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|
unsigned int limited_regs; /* allow limited registers only */
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DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
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};
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struct _snd_ac97 {
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/* -- lowlevel (hardware) driver specific -- */
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struct snd_ac97_build_ops * build_ops;
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void *private_data;
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void (*private_free) (ac97_t *ac97);
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|
/* --- */
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|
ac97_bus_t *bus;
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|
struct pci_dev *pci; /* assigned PCI device - used for quirks */
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|
snd_info_entry_t *proc;
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|
snd_info_entry_t *proc_regs;
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|
unsigned short subsystem_vendor;
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|
unsigned short subsystem_device;
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|
struct semaphore reg_mutex;
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|
struct semaphore page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */
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|
unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
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|
unsigned short addr; /* physical address of codec [0-3] */
|
|
unsigned int id; /* identification of codec */
|
|
unsigned short caps; /* capabilities (register 0) */
|
|
unsigned short ext_id; /* extended feature identification (register 28) */
|
|
unsigned short ext_mid; /* extended modem ID (register 3C) */
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|
unsigned int scaps; /* driver capabilities */
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|
unsigned int flags; /* specific code */
|
|
unsigned int rates[6]; /* see AC97_RATES_* defines */
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|
unsigned int spdif_status;
|
|
unsigned short regs[0x80]; /* register cache */
|
|
unsigned int limited_regs; /* allow limited registers only */
|
|
DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
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|
union { /* vendor specific code */
|
|
struct {
|
|
unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69
|
|
unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69
|
|
unsigned short id[3]; // codec IDs (lower 16-bit word)
|
|
unsigned short pcmreg[3]; // PCM registers
|
|
unsigned short codec_cfg[3]; // CODEC_CFG bits
|
|
} ad18xx;
|
|
unsigned int dev_flags; /* device specific */
|
|
} spec;
|
|
/* jack-sharing info */
|
|
unsigned char indep_surround;
|
|
unsigned char channel_mode;
|
|
struct device dev;
|
|
};
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|
|
|
#define to_ac97_t(d) container_of(d, struct _snd_ac97, dev)
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|
|
|
/* conditions */
|
|
static inline int ac97_is_audio(ac97_t * ac97)
|
|
{
|
|
return (ac97->scaps & AC97_SCAP_AUDIO);
|
|
}
|
|
static inline int ac97_is_modem(ac97_t * ac97)
|
|
{
|
|
return (ac97->scaps & AC97_SCAP_MODEM);
|
|
}
|
|
static inline int ac97_is_rev22(ac97_t * ac97)
|
|
{
|
|
return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22;
|
|
}
|
|
static inline int ac97_can_amap(ac97_t * ac97)
|
|
{
|
|
return (ac97->ext_id & AC97_EI_AMAP) != 0;
|
|
}
|
|
static inline int ac97_can_spdif(ac97_t * ac97)
|
|
{
|
|
return (ac97->ext_id & AC97_EI_SPDIF) != 0;
|
|
}
|
|
|
|
/* functions */
|
|
int snd_ac97_bus(snd_card_t *card, int num, ac97_bus_ops_t *ops, void *private_data, ac97_bus_t **rbus); /* create new AC97 bus */
|
|
int snd_ac97_mixer(ac97_bus_t *bus, ac97_template_t *template, ac97_t **rac97); /* create mixer controls */
|
|
const char *snd_ac97_get_short_name(ac97_t *ac97);
|
|
|
|
void snd_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short value);
|
|
unsigned short snd_ac97_read(ac97_t *ac97, unsigned short reg);
|
|
void snd_ac97_write_cache(ac97_t *ac97, unsigned short reg, unsigned short value);
|
|
int snd_ac97_update(ac97_t *ac97, unsigned short reg, unsigned short value);
|
|
int snd_ac97_update_bits(ac97_t *ac97, unsigned short reg, unsigned short mask, unsigned short value);
|
|
#ifdef CONFIG_PM
|
|
void snd_ac97_suspend(ac97_t *ac97);
|
|
void snd_ac97_resume(ac97_t *ac97);
|
|
#endif
|
|
|
|
/* quirk types */
|
|
enum {
|
|
AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */
|
|
AC97_TUNE_NONE = 0, /* nothing extra to do */
|
|
AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */
|
|
AC97_TUNE_SWAP_HP, /* swap headphone and master controls */
|
|
AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */
|
|
AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */
|
|
AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */
|
|
AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */
|
|
AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */
|
|
};
|
|
|
|
struct ac97_quirk {
|
|
unsigned short subvendor; /* PCI subsystem vendor id */
|
|
unsigned short subdevice; /* PCI sybsystem device id */
|
|
unsigned short mask; /* device id bit mask, 0 = accept all */
|
|
unsigned int codec_id; /* codec id (if any), 0 = accept all */
|
|
const char *name; /* name shown as info */
|
|
int type; /* quirk type above */
|
|
};
|
|
|
|
int snd_ac97_tune_hardware(ac97_t *ac97, struct ac97_quirk *quirk, const char *override);
|
|
int snd_ac97_set_rate(ac97_t *ac97, int reg, unsigned int rate);
|
|
|
|
int snd_ac97_pcm_assign(ac97_bus_t *ac97,
|
|
unsigned short pcms_count,
|
|
const struct ac97_pcm *pcms);
|
|
int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate,
|
|
enum ac97_pcm_cfg cfg, unsigned short slots);
|
|
int snd_ac97_pcm_close(struct ac97_pcm *pcm);
|
|
int snd_ac97_pcm_double_rate_rules(snd_pcm_runtime_t *runtime);
|
|
|
|
struct ac97_enum {
|
|
unsigned char reg;
|
|
unsigned char shift_l;
|
|
unsigned char shift_r;
|
|
unsigned short mask;
|
|
const char **texts;
|
|
};
|
|
|
|
/* ad hoc AC97 device driver access */
|
|
extern struct bus_type ac97_bus_type;
|
|
|
|
#endif /* __SOUND_AC97_CODEC_H */
|