2ef9481e66
This patch removes all self references and fixes references to files in the now defunct arch/ppc64 tree. I think this accomplises everything wanted, though there might be a few references I missed. Signed-off-by: Jon Mason <jdmason@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
258 lines
6.9 KiB
C
258 lines
6.9 KiB
C
/*
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* SBC82XX platform support
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*
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* Author: Guy Streeter <streeter@redhat.com>
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*
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* Derived from: est8260_setup.c by Allen Curtis, ONZ
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*
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* Copyright 2004 Red Hat, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/mpc8260.h>
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#include <asm/machdep.h>
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#include <asm/io.h>
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#include <asm/todc.h>
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#include <asm/immap_cpm2.h>
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#include <asm/pci.h>
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static void (*callback_init_IRQ)(void);
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extern unsigned char __res[sizeof(bd_t)];
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extern void (*late_time_init)(void);
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#ifdef CONFIG_GEN_RTC
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TODC_ALLOC();
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/*
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* Timer init happens before mem_init but after paging init, so we cannot
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* directly use ioremap() at that time.
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* late_time_init() is call after paging init.
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*/
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static void sbc82xx_time_init(void)
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{
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volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
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/* Set up CS11 for RTC chip */
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mc->memc_br11=0;
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mc->memc_or11=0xffff0836;
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mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
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TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
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todc_info->nvram_data =
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(unsigned int)ioremap(todc_info->nvram_data, 0x2000);
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BUG_ON(!todc_info->nvram_data);
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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todc_time_init();
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}
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#endif /* CONFIG_GEN_RTC */
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static volatile char *sbc82xx_i8259_map;
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static char sbc82xx_i8259_mask = 0xff;
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static DEFINE_SPINLOCK(sbc82xx_i8259_lock);
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static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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irq_nr -= NR_SIU_INTS;
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spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
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sbc82xx_i8259_mask |= 1 << irq_nr;
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(void) sbc82xx_i8259_map[1]; /* Dummy read */
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sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
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sbc82xx_i8259_map[0] = 0x20; /* OCW2: Non-specific EOI */
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spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
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}
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static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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irq_nr -= NR_SIU_INTS;
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spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
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sbc82xx_i8259_mask |= 1 << irq_nr;
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sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
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spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
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}
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static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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irq_nr -= NR_SIU_INTS;
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spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
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sbc82xx_i8259_mask &= ~(1 << irq_nr);
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sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
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spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
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}
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static void sbc82xx_i8259_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq].action)
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sbc82xx_i8259_unmask_irq(irq);
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}
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struct hw_interrupt_type sbc82xx_i8259_ic = {
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.typename = " i8259 ",
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.enable = sbc82xx_i8259_unmask_irq,
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.disable = sbc82xx_i8259_mask_irq,
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.ack = sbc82xx_i8259_mask_and_ack_irq,
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.end = sbc82xx_i8259_end_irq,
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};
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static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id, struct pt_regs *regs)
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{
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spin_lock(&sbc82xx_i8259_lock);
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sbc82xx_i8259_map[0] = 0x0c; /* OCW3: Read IR register on RD# pulse */
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irq = sbc82xx_i8259_map[0] & 7; /* Read IRR */
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if (irq == 7) {
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/* Possible spurious interrupt */
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int isr;
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sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */
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isr = sbc82xx_i8259_map[0]; /* Read ISR */
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if (!(isr & 0x80)) {
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printk(KERN_INFO "Spurious i8259 interrupt\n");
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return IRQ_HANDLED;
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}
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}
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__do_IRQ(NR_SIU_INTS + irq, regs);
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return IRQ_HANDLED;
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}
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static struct irqaction sbc82xx_i8259_irqaction = {
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.handler = sbc82xx_i8259_demux,
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.flags = SA_INTERRUPT,
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.mask = CPU_MASK_NONE,
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.name = "i8259 demux",
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};
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void __init sbc82xx_init_IRQ(void)
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{
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volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
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volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
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int i;
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callback_init_IRQ();
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/* u-boot doesn't always set the board up correctly */
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mc->memc_br5 = 0;
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mc->memc_or5 = 0xfff00856;
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mc->memc_br5 = 0x22000801;
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sbc82xx_i8259_map = ioremap(0x22008000, 2);
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if (!sbc82xx_i8259_map) {
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printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
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return;
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}
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/* Set up the interrupt handlers for the i8259 IRQs */
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for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
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irq_desc[i].handler = &sbc82xx_i8259_ic;
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irq_desc[i].status |= IRQ_LEVEL;
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}
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/* make IRQ6 level sensitive */
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ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
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irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
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/* Initialise the i8259 */
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sbc82xx_i8259_map[0] = 0x1b; /* ICW1: Level, no cascade, ICW4 */
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sbc82xx_i8259_map[1] = 0x00; /* ICW2: vector base */
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/* No ICW3 (no cascade) */
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sbc82xx_i8259_map[1] = 0x01; /* ICW4: 8086 mode, normal EOI */
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sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */
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sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
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/* Request cascade IRQ */
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if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) {
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printk("Installation of i8259 IRQ demultiplexer failed.\n");
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}
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}
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static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
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unsigned char pin)
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{
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static char pci_irq_table[][4] = {
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 16 - PMC slot */
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{ SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1, -1 }, /* IDSEL 17 - CardBus */
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{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
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};
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const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev)
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{
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uint32_t ctrl;
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if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0))
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return;
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printk(KERN_INFO "Setting up CardBus controller\n");
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/* Set P2CCLK bit in System Control Register */
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pci_read_config_dword(pdev, 0x80, &ctrl);
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ctrl |= (1<<27);
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pci_write_config_dword(pdev, 0x80, ctrl);
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/* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */
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pci_write_config_dword(pdev, 0x8c, 0x00c01d22);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus);
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void __init
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m82xx_board_init(void)
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{
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/* u-boot may be using one of the FCC Ethernet devices.
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Use the MAC address to the SCC. */
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__res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
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/* Anything special for this platform */
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callback_init_IRQ = ppc_md.init_IRQ;
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ppc_md.init_IRQ = sbc82xx_init_IRQ;
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ppc_md.pci_map_irq = sbc82xx_pci_map_irq;
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#ifdef CONFIG_GEN_RTC
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ppc_md.time_init = NULL;
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ppc_md.get_rtc_time = NULL;
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ppc_md.set_rtc_time = NULL;
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ppc_md.nvram_read_val = NULL;
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ppc_md.nvram_write_val = NULL;
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late_time_init = sbc82xx_time_init;
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#endif /* CONFIG_GEN_RTC */
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}
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