62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/* Copyright (C) 1999,2001
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*
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* Author: J.E.J.Bottomley@HansenPartnership.com
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*
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* Standard include definitions for the NCR Voyager Interrupt Controller */
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/* The eight CPI vectors. To activate a CPI, you write a bit mask
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* corresponding to the processor set to be interrupted into the
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* relevant register. That set of CPUs will then be interrupted with
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* the CPI */
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static const int VIC_CPI_Registers[] =
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{0xFC00, 0xFC01, 0xFC08, 0xFC09,
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0xFC10, 0xFC11, 0xFC18, 0xFC19 };
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#define VIC_PROC_WHO_AM_I 0xfc29
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# define QUAD_IDENTIFIER 0xC0
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# define EIGHT_SLOT_IDENTIFIER 0xE0
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#define QIC_EXTENDED_PROCESSOR_SELECT 0xFC72
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#define VIC_CPI_BASE_REGISTER 0xFC41
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#define VIC_PROCESSOR_ID 0xFC21
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# define VIC_CPU_MASQUERADE_ENABLE 0x8
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#define VIC_CLAIM_REGISTER_0 0xFC38
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#define VIC_CLAIM_REGISTER_1 0xFC39
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#define VIC_REDIRECT_REGISTER_0 0xFC60
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#define VIC_REDIRECT_REGISTER_1 0xFC61
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#define VIC_PRIORITY_REGISTER 0xFC20
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#define VIC_PRIMARY_MC_BASE 0xFC48
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#define VIC_SECONDARY_MC_BASE 0xFC49
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#define QIC_PROCESSOR_ID 0xFC71
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# define QIC_CPUID_ENABLE 0x08
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#define QIC_VIC_CPI_BASE_REGISTER 0xFC79
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#define QIC_CPI_BASE_REGISTER 0xFC7A
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#define QIC_MASK_REGISTER0 0xFC80
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/* NOTE: these are masked high, enabled low */
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# define QIC_PERF_TIMER 0x01
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# define QIC_LPE 0x02
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# define QIC_SYS_INT 0x04
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# define QIC_CMN_INT 0x08
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/* at the moment, just enable CMN_INT, disable SYS_INT */
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# define QIC_DEFAULT_MASK0 (~(QIC_CMN_INT /* | VIC_SYS_INT */))
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#define QIC_MASK_REGISTER1 0xFC81
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# define QIC_BOOT_CPI_MASK 0xFE
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/* Enable CPI's 1-6 inclusive */
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# define QIC_CPI_ENABLE 0x81
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#define QIC_INTERRUPT_CLEAR0 0xFC8A
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#define QIC_INTERRUPT_CLEAR1 0xFC8B
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/* this is where we place the CPI vectors */
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#define VIC_DEFAULT_CPI_BASE 0xC0
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/* this is where we place the QIC CPI vectors */
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#define QIC_DEFAULT_CPI_BASE 0xD0
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#define VIC_BOOT_INTERRUPT_MASK 0xfe
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extern void smp_vic_timer_interrupt(struct pt_regs *regs);
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