213 lines
4.6 KiB
C
213 lines
4.6 KiB
C
/* internal Peripherals Register address define */
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/* CPU: H8/306x */
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#if !defined(__REGS_H8306x__)
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#define __REGS_H8306x__
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#if defined(__KERNEL__)
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#define DASTCR 0xFEE01A
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#define DADR0 0xFEE09C
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#define DADR1 0xFEE09D
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#define DACR 0xFEE09E
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#define ADDRAH 0xFFFFE0
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#define ADDRAL 0xFFFFE1
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#define ADDRBH 0xFFFFE2
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#define ADDRBL 0xFFFFE3
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#define ADDRCH 0xFFFFE4
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#define ADDRCL 0xFFFFE5
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#define ADDRDH 0xFFFFE6
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#define ADDRDL 0xFFFFE7
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#define ADCSR 0xFFFFE8
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#define ADCR 0xFFFFE9
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#define BRCR 0xFEE013
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#define ADRCR 0xFEE01E
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#define CSCR 0xFEE01F
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#define ABWCR 0xFEE020
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#define ASTCR 0xFEE021
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#define WCRH 0xFEE022
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#define WCRL 0xFEE023
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#define BCR 0xFEE024
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#define DRCRA 0xFEE026
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#define DRCRB 0xFEE027
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#define RTMCSR 0xFEE028
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#define RTCNT 0xFEE029
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#define RTCOR 0xFEE02A
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#define MAR0AR 0xFFFF20
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#define MAR0AE 0xFFFF21
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#define MAR0AH 0xFFFF22
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#define MAR0AL 0xFFFF23
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#define ETCR0AL 0xFFFF24
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#define ETCR0AH 0xFFFF25
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#define IOAR0A 0xFFFF26
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#define DTCR0A 0xFFFF27
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#define MAR0BR 0xFFFF28
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#define MAR0BE 0xFFFF29
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#define MAR0BH 0xFFFF2A
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#define MAR0BL 0xFFFF2B
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#define ETCR0BL 0xFFFF2C
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#define ETCR0BH 0xFFFF2D
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#define IOAR0B 0xFFFF2E
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#define DTCR0B 0xFFFF2F
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#define MAR1AR 0xFFFF30
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#define MAR1AE 0xFFFF31
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#define MAR1AH 0xFFFF32
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#define MAR1AL 0xFFFF33
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#define ETCR1AL 0xFFFF34
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#define ETCR1AH 0xFFFF35
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#define IOAR1A 0xFFFF36
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#define DTCR1A 0xFFFF37
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#define MAR1BR 0xFFFF38
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#define MAR1BE 0xFFFF39
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#define MAR1BH 0xFFFF3A
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#define MAR1BL 0xFFFF3B
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#define ETCR1BL 0xFFFF3C
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#define ETCR1BH 0xFFFF3D
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#define IOAR1B 0xFFFF3E
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#define DTCR1B 0xFFFF3F
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#define ISCR 0xFEE014
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#define IER 0xFEE015
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#define ISR 0xFEE016
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#define IPRA 0xFEE018
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#define IPRB 0xFEE019
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#define P1DDR 0xFEE000
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#define P2DDR 0xFEE001
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#define P3DDR 0xFEE002
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#define P4DDR 0xFEE003
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#define P5DDR 0xFEE004
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#define P6DDR 0xFEE005
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/*#define P7DDR 0xFEE006*/
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#define P8DDR 0xFEE007
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#define P9DDR 0xFEE008
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#define PADDR 0xFEE009
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#define PBDDR 0xFEE00A
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#define P1DR 0xFFFFD0
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#define P2DR 0xFFFFD1
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#define P3DR 0xFFFFD2
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#define P4DR 0xFFFFD3
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#define P5DR 0xFFFFD4
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#define P6DR 0xFFFFD5
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/*#define P7DR 0xFFFFD6*/
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#define P8DR 0xFFFFD7
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#define P9DR 0xFFFFD8
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#define PADR 0xFFFFD9
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#define PBDR 0xFFFFDA
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#define P2CR 0xFEE03C
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#define P4CR 0xFEE03E
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#define P5CR 0xFEE03F
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#define SMR0 0xFFFFB0
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#define BRR0 0xFFFFB1
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#define SCR0 0xFFFFB2
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#define TDR0 0xFFFFB3
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#define SSR0 0xFFFFB4
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#define RDR0 0xFFFFB5
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#define SCMR0 0xFFFFB6
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#define SMR1 0xFFFFB8
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#define BRR1 0xFFFFB9
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#define SCR1 0xFFFFBA
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#define TDR1 0xFFFFBB
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#define SSR1 0xFFFFBC
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#define RDR1 0xFFFFBD
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#define SCMR1 0xFFFFBE
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#define SMR2 0xFFFFC0
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#define BRR2 0xFFFFC1
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#define SCR2 0xFFFFC2
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#define TDR2 0xFFFFC3
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#define SSR2 0xFFFFC4
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#define RDR2 0xFFFFC5
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#define SCMR2 0xFFFFC6
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#define MDCR 0xFEE011
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#define SYSCR 0xFEE012
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#define DIVCR 0xFEE01B
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#define MSTCRH 0xFEE01C
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#define MSTCRL 0xFEE01D
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#define FLMCR1 0xFEE030
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#define FLMCR2 0xFEE031
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#define EBR1 0xFEE032
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#define EBR2 0xFEE033
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#define RAMCR 0xFEE077
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#define TSTR 0xFFFF60
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#define TSNC 0XFFFF61
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#define TMDR 0xFFFF62
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#define TOLR 0xFFFF63
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#define TISRA 0xFFFF64
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#define TISRB 0xFFFF65
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#define TISRC 0xFFFF66
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#define TCR0 0xFFFF68
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#define TIOR0 0xFFFF69
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#define TCNT0H 0xFFFF6A
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#define TCNT0L 0xFFFF6B
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#define GRA0H 0xFFFF6C
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#define GRA0L 0xFFFF6D
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#define GRB0H 0xFFFF6E
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#define GRB0L 0xFFFF6F
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#define TCR1 0xFFFF70
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#define TIOR1 0xFFFF71
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#define TCNT1H 0xFFFF72
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#define TCNT1L 0xFFFF73
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#define GRA1H 0xFFFF74
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#define GRA1L 0xFFFF75
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#define GRB1H 0xFFFF76
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#define GRB1L 0xFFFF77
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#define TCR3 0xFFFF78
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#define TIOR3 0xFFFF79
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#define TCNT3H 0xFFFF7A
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#define TCNT3L 0xFFFF7B
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#define GRA3H 0xFFFF7C
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#define GRA3L 0xFFFF7D
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#define GRB3H 0xFFFF7E
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#define GRB3L 0xFFFF7F
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#define _8TCR0 0xFFFF80
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#define _8TCR1 0xFFFF81
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#define _8TCSR0 0xFFFF82
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#define _8TCSR1 0xFFFF83
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#define TCORA0 0xFFFF84
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#define TCORA1 0xFFFF85
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#define TCORB0 0xFFFF86
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#define TCORB1 0xFFFF87
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#define _8TCNT0 0xFFFF88
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#define _8TCNT1 0xFFFF89
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#define _8TCR2 0xFFFF90
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#define _8TCR3 0xFFFF91
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#define _8TCSR2 0xFFFF92
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#define _8TCSR3 0xFFFF93
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#define TCORA2 0xFFFF94
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#define TCORA3 0xFFFF95
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#define TCORB2 0xFFFF96
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#define TCORB3 0xFFFF97
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#define _8TCNT2 0xFFFF98
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#define _8TCNT3 0xFFFF99
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#define TCSR 0xFFFF8C
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#define TCNT 0xFFFF8D
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#define RSTCSR 0xFFFF8F
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#define TPMR 0xFFFFA0
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#define TPCR 0xFFFFA1
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#define NDERB 0xFFFFA2
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#define NDERA 0xFFFFA3
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#define NDRB1 0xFFFFA4
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#define NDRA1 0xFFFFA5
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#define NDRB2 0xFFFFA6
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#define NDRA2 0xFFFFA7
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#define TCSR 0xFFFF8C
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#define TCNT 0xFFFF8D
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#define RSTCSRW 0xFFFF8E
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#define RSTCSRR 0xFFFF8F
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#endif /* __KERNEL__ */
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#endif /* __REGS_H8306x__ */
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