1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
120 lines
5.0 KiB
C
120 lines
5.0 KiB
C
/****************************************************************************/
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/*
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* mcfdebug.h -- ColdFire Debug Module support.
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*
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* (C) Copyright 2001, Lineo Inc. (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef mcfdebug_h
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#define mcfdebug_h
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/****************************************************************************/
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#include <linux/config.h>
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/* Define the debug module registers */
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#define MCFDEBUG_CSR 0x0 /* Configuration status */
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#define MCFDEBUG_BAAR 0x5 /* BDM address attribute */
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#define MCFDEBUG_AATR 0x6 /* Address attribute trigger */
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#define MCFDEBUG_TDR 0x7 /* Trigger definition */
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#define MCFDEBUG_PBR 0x8 /* PC breakpoint */
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#define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */
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#define MCFDEBUG_ABHR 0xc /* High address breakpoint */
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#define MCFDEBUG_ABLR 0xd /* Low address breakpoint */
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#define MCFDEBUG_DBR 0xe /* Data breakpoint */
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#define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */
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/* Define some handy constants for the trigger definition register */
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#define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */
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#define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */
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#define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */
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#define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */
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#define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */
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#define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */
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#define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */
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#define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */
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#define MCFDEBUG_TDR_EDLW2 0x10000000
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#define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */
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#define MCFDEBUG_TDR_EDWL2 0x08000000
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#define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */
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#define MCFDEBUG_TDR_EDWU2 0x04000000
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#define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */
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#define MCFDEBUG_TDR_EDLL2 0x02000000
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#define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */
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#define MCFDEBUG_TDR_EDLM2 0x01000000
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#define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */
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#define MCFDEBUG_TDR_EDUM2 0x00800000
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#define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */
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#define MCFDEBUG_TDR_EDUU2 0x00400000
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#define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */
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#define MCFDEBUG_TDR_DI2 0x00200000
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#define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */
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#define MCFDEBUG_TDR_EAI2 0x00100000
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#define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */
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#define MCFDEBUG_TDR_EAR2 0x00080000
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#define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */
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#define MCFDEBUG_TDR_EAL2 0x00040000
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#define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */
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#define MCFDEBUG_TDR_EPC2 0x00020000
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#define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */
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#define MCFDEBUG_TDR_PCI2 0x00010000
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/* Constants for the address attribute trigger register */
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#define MCFDEBUG_AAR_RESET 0x00000005
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/* Fields not yet implemented */
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/* And some definitions for the writable sections of the CSR */
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#define MCFDEBUG_CSR_RESET 0x00100000
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#define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */
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#define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */
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#define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */
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#define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */
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#define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */
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#define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */
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#define MCFDEBUG_CSR_DDC_WRITE 0x00001000
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#define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */
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#define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */
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#define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */
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#define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */
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#define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */
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#define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */
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#define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */
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/* Constants for the BDM address attribute register */
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#define MCFDEBUG_BAAR_RESET 0x00000005
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/* Fields not yet implemented */
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/* This routine wrappers up the wdebug asm instruction so that the register
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* and value can be relatively easily specified. The biggest hassle here is
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* that the debug module instructions (2 longs) must be long word aligned and
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* some pointer fiddling is performed to ensure this.
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*/
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extern inline void wdebug(int reg, unsigned long data) {
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unsigned short dbg_spc[6];
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unsigned short *dbg;
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// Force alignment to long word boundary
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dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc);
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// Build up the debug instruction
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dbg[0] = 0x2c80 | (reg & 0xf);
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dbg[1] = (data >> 16) & 0xffff;
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dbg[2] = data & 0xffff;
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dbg[3] = 0;
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// Perform the wdebug instruction
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#if 0
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// This strain is for gas which doesn't have the wdebug instructions defined
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asm( "move.l %0, %%a0\n\t"
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".word 0xfbd0\n\t"
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".word 0x0003\n\t"
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:: "g" (dbg) : "a0");
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#else
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// And this is for when it does
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asm( "wdebug (%0)" :: "a" (dbg));
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#endif
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}
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#endif
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