5dfa9c1b4f
This patch updates NEC VR4100 series CPU-PCI bridge support. Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
235 lines
6.0 KiB
C
235 lines
6.0 KiB
C
/*
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* include/asm-mips/vr41xx/vr41xx.h
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*
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* Include file for NEC VR4100 series.
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*
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* Copyright (C) 1999 Michael Klar
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* Copyright (C) 2001, 2002 Paul Mundt
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* Copyright (C) 2002 MontaVista Software, Inc.
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* Copyright (C) 2002 TimeSys Corp.
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* Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __NEC_VR41XX_H
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#define __NEC_VR41XX_H
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#include <linux/interrupt.h>
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/*
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* CPU Revision
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*/
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/* VR4122 0x00000c70-0x00000c72 */
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#define PRID_VR4122_REV1_0 0x00000c70
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#define PRID_VR4122_REV2_0 0x00000c70
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#define PRID_VR4122_REV2_1 0x00000c70
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#define PRID_VR4122_REV3_0 0x00000c71
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#define PRID_VR4122_REV3_1 0x00000c72
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/* VR4181A 0x00000c73-0x00000c7f */
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#define PRID_VR4181A_REV1_0 0x00000c73
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#define PRID_VR4181A_REV1_1 0x00000c74
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/* VR4131 0x00000c80-0x00000c83 */
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#define PRID_VR4131_REV1_2 0x00000c80
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#define PRID_VR4131_REV2_0 0x00000c81
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#define PRID_VR4131_REV2_1 0x00000c82
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#define PRID_VR4131_REV2_2 0x00000c83
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/* VR4133 0x00000c84- */
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#define PRID_VR4133 0x00000c84
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/*
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* Bus Control Uint
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*/
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extern unsigned long vr41xx_calculate_clock_frequency(void);
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extern unsigned long vr41xx_get_vtclock_frequency(void);
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extern unsigned long vr41xx_get_tclock_frequency(void);
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/*
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* Clock Mask Unit
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*/
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typedef enum {
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PIU_CLOCK,
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SIU_CLOCK,
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AIU_CLOCK,
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KIU_CLOCK,
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FIR_CLOCK,
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DSIU_CLOCK,
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CSI_CLOCK,
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PCIU_CLOCK,
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HSP_CLOCK,
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PCI_CLOCK,
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CEU_CLOCK,
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ETHER0_CLOCK,
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ETHER1_CLOCK
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} vr41xx_clock_t;
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extern void vr41xx_supply_clock(vr41xx_clock_t clock);
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extern void vr41xx_mask_clock(vr41xx_clock_t clock);
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/*
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* Interrupt Control Unit
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*/
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/* CPU core Interrupt Numbers */
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#define MIPS_CPU_IRQ_BASE 0
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#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
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#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
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#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
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#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2)
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#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3)
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#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4)
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#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5)
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#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6)
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#define TIMER_IRQ MIPS_CPU_IRQ(7)
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/* SYINT1 Interrupt Numbers */
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#define SYSINT1_IRQ_BASE 8
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#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
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#define BATTRY_IRQ SYSINT1_IRQ(0)
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#define POWER_IRQ SYSINT1_IRQ(1)
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#define RTCLONG1_IRQ SYSINT1_IRQ(2)
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#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
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/* RFU */
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#define PIU_IRQ SYSINT1_IRQ(5)
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#define AIU_IRQ SYSINT1_IRQ(6)
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#define KIU_IRQ SYSINT1_IRQ(7)
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#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8)
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#define SIU_IRQ SYSINT1_IRQ(9)
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#define BUSERR_IRQ SYSINT1_IRQ(10)
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#define SOFTINT_IRQ SYSINT1_IRQ(11)
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#define CLKRUN_IRQ SYSINT1_IRQ(12)
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#define DOZEPIU_IRQ SYSINT1_IRQ(13)
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#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
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/* SYSINT2 Interrupt Numbers */
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#define SYSINT2_IRQ_BASE 24
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#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
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#define RTCLONG2_IRQ SYSINT2_IRQ(0)
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#define LED_IRQ SYSINT2_IRQ(1)
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#define HSP_IRQ SYSINT2_IRQ(2)
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#define TCLOCK_IRQ SYSINT2_IRQ(3)
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#define FIR_IRQ SYSINT2_IRQ(4)
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#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
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#define DSIU_IRQ SYSINT2_IRQ(5)
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#define PCI_IRQ SYSINT2_IRQ(6)
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#define SCU_IRQ SYSINT2_IRQ(7)
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#define CSI_IRQ SYSINT2_IRQ(8)
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#define BCU_IRQ SYSINT2_IRQ(9)
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#define ETHERNET_IRQ SYSINT2_IRQ(10)
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#define SYSINT2_IRQ_LAST ETHERNET_IRQ
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/* GIU Interrupt Numbers */
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#define GIU_IRQ_BASE 40
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#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
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#define GIU_IRQ_LAST GIU_IRQ(31)
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#define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */
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extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
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extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
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#define PIUINT_COMMAND 0x0040
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#define PIUINT_DATA 0x0020
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#define PIUINT_PAGE1 0x0010
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#define PIUINT_PAGE0 0x0008
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#define PIUINT_DATALOST 0x0004
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#define PIUINT_STATUSCHANGE 0x0001
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extern void vr41xx_enable_piuint(uint16_t mask);
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extern void vr41xx_disable_piuint(uint16_t mask);
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#define AIUINT_INPUT_DMAEND 0x0800
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#define AIUINT_INPUT_DMAHALT 0x0400
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#define AIUINT_INPUT_DATALOST 0x0200
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#define AIUINT_INPUT_DATA 0x0100
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#define AIUINT_OUTPUT_DMAEND 0x0008
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#define AIUINT_OUTPUT_DMAHALT 0x0004
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#define AIUINT_OUTPUT_NODATA 0x0002
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extern void vr41xx_enable_aiuint(uint16_t mask);
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extern void vr41xx_disable_aiuint(uint16_t mask);
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#define KIUINT_DATALOST 0x0004
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#define KIUINT_DATAREADY 0x0002
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#define KIUINT_SCAN 0x0001
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extern void vr41xx_enable_kiuint(uint16_t mask);
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extern void vr41xx_disable_kiuint(uint16_t mask);
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#define DSIUINT_CTS 0x0800
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#define DSIUINT_RXERR 0x0400
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#define DSIUINT_RX 0x0200
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#define DSIUINT_TX 0x0100
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#define DSIUINT_ALL 0x0f00
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extern void vr41xx_enable_dsiuint(uint16_t mask);
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extern void vr41xx_disable_dsiuint(uint16_t mask);
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#define FIRINT_UNIT 0x0010
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#define FIRINT_RX_DMAEND 0x0008
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#define FIRINT_RX_DMAHALT 0x0004
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#define FIRINT_TX_DMAEND 0x0002
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#define FIRINT_TX_DMAHALT 0x0001
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extern void vr41xx_enable_firint(uint16_t mask);
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extern void vr41xx_disable_firint(uint16_t mask);
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extern void vr41xx_enable_pciint(void);
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extern void vr41xx_disable_pciint(void);
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extern void vr41xx_enable_scuint(void);
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extern void vr41xx_disable_scuint(void);
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#define CSIINT_TX_DMAEND 0x0040
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#define CSIINT_TX_DMAHALT 0x0020
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#define CSIINT_TX_DATA 0x0010
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#define CSIINT_TX_FIFOEMPTY 0x0008
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#define CSIINT_RX_DMAEND 0x0004
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#define CSIINT_RX_DMAHALT 0x0002
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#define CSIINT_RX_FIFOEMPTY 0x0001
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extern void vr41xx_enable_csiint(uint16_t mask);
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extern void vr41xx_disable_csiint(uint16_t mask);
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extern void vr41xx_enable_bcuint(void);
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extern void vr41xx_disable_bcuint(void);
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/*
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* General-Purpose I/O Unit
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*/
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enum {
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TRIGGER_LEVEL,
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TRIGGER_EDGE,
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TRIGGER_EDGE_FALLING,
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TRIGGER_EDGE_RISING
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};
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enum {
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SIGNAL_THROUGH,
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SIGNAL_HOLD
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};
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extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
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enum {
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LEVEL_LOW,
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LEVEL_HIGH
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};
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extern void vr41xx_set_irq_level(int pin, int level);
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enum {
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PIO_INPUT,
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PIO_OUTPUT
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};
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enum {
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DATA_LOW,
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DATA_HIGH
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};
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#endif /* __NEC_VR41XX_H */
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