a240a46964
Support for the GT-64120-based Wind River 4KC PPMC Evaluation board. Signed-off-by: Rongkai.Zhan <Rongkai.zhan@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/*
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* This is a direct copy of the ev96100.h file, with a global
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* search and replace. The numbers are the same.
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*
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* The reason I'm duplicating this is so that the 64120/96100
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* defines won't be confusing in the source code.
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*/
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#ifndef __ASM_MIPS_GT64120_H
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#define __ASM_MIPS_GT64120_H
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/*
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* This is the CPU physical memory map of PPMC Board:
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*
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* 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
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* 0x1C000000-0x1C000000 - LED (CS0)
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* 0x1C800000-0x1C800007 - UART 16550 port (CS1)
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* 0x1F000000-0x1F000000 - MailBox (CS3)
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* 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
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*/
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#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
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#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
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#define WRPPMC_UART16550_BASE 0x1C800000
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#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
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#define WRPPMC_LED_BASE 0x1C000000
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#define WRPPMC_MBOX_BASE 0x1F000000
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#define WRPPMC_BOOTROM_BASE 0x1FC00000
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#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
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#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
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#define WRPPMC_UART16550_IRQ 6
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#define WRPPMC_PCI_INTA_IRQ 3
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/*
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* PCI Bus I/O and Memory resources allocation
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*
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* NOTE: We only have PCI_0 hose interface
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*/
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#define GT_PCI_MEM_BASE 0x13000000UL
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#define GT_PCI_MEM_SIZE 0x02000000UL
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#define GT_PCI_IO_BASE 0x11000000UL
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#define GT_PCI_IO_SIZE 0x02000000UL
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#define GT_ISA_IO_BASE PCI_IO_BASE
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/*
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* PCI interrupts will come in on either the INTA or INTD interrups lines,
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* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
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* boards, they all either come in on IntD or they all come in on IntA, they
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* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
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* "requested" interrupt numbers and go through the list whenever we get an
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* IntA/D.
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*
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* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
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* INTD is 11.
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*/
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#define GT_TIMER 4
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#define GT_INTA 2
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#define GT_INTD 5
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#ifndef __ASSEMBLY__
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/*
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* GT64120 internal register space base address
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*/
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extern unsigned long gt64120_base;
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#define GT64120_BASE (gt64120_base)
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/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
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#undef WRPPMC_EARLY_DEBUG
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#ifdef WRPPMC_EARLY_DEBUG
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extern void wrppmc_led_on(int mask);
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extern void wrppmc_led_off(int mask);
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extern void wrppmc_early_printk(const char *fmt, ...);
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#else
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#define wrppmc_early_printk(fmt, ...) do {} while (0)
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#endif /* WRPPMC_EARLY_DEBUG */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_MIPS_GT64120_H */
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