1dbae815a7
Patch from Tony Lindgren This patch adds support for omap24xx series of processors. The files live in arch/arm/mach-omap2, and share common files with omap15xx and omap16xx processors in arch/arm/plat-omap. Omap24xx support was originally added for 2.6.9 by TI. This code was then improved and integrated to share common code with omap15xx and omap16xx processors by various omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak, Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah et al. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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* linux/arch/arm/mach-omap/omap2/irq.c
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*
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* Interrupt handler for OMAP2 boards.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/config.h>
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#include <linux/interrupt.h>
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#include <asm/hardware.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#define INTC_REVISION 0x0000
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#define INTC_SYSCONFIG 0x0010
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#define INTC_SYSSTATUS 0x0014
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#define INTC_CONTROL 0x0048
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#define INTC_MIR_CLEAR0 0x0088
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#define INTC_MIR_SET0 0x008c
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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* controller is identified as its own "bank". Register definitions are
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* fairly consistent for each bank, but not all registers are implemented
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* for each bank.. when in doubt, consult the TRM.
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*/
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static struct omap_irq_bank {
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unsigned long base_reg;
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unsigned int nr_irqs;
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} __attribute__ ((aligned(4))) irq_banks[] = {
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{
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/* MPU INTC */
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.base_reg = OMAP24XX_IC_BASE,
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.nr_irqs = 96,
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}, {
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/* XXX: DSP INTC */
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#if 0
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/*
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* Commented out for now until we fix the IVA clocking
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*/
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#ifdef CONFIG_ARCH_OMAP2420
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}, {
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/* IVA INTC (2420 only) */
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.base_reg = OMAP24XX_IVA_INTC_BASE,
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.nr_irqs = 16, /* Actually 32, but only 16 are used */
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#endif
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#endif
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}
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};
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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static void omap_ack_irq(unsigned int irq)
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{
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omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
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}
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static void omap_mask_irq(unsigned int irq)
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{
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int offset = (irq >> 5) << 5;
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if (irq >= 64) {
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irq %= 64;
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} else if (irq >= 32) {
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irq %= 32;
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}
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omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
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}
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static void omap_unmask_irq(unsigned int irq)
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{
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int offset = (irq >> 5) << 5;
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if (irq >= 64) {
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irq %= 64;
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} else if (irq >= 32) {
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irq %= 32;
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}
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omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
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}
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static void omap_mask_ack_irq(unsigned int irq)
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{
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omap_mask_irq(irq);
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omap_ack_irq(irq);
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}
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static struct irqchip omap_irq_chip = {
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.ack = omap_mask_ack_irq,
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.mask = omap_mask_irq,
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.unmask = omap_unmask_irq,
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};
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static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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{
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unsigned long tmp;
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tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff;
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printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
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"(revision %ld.%ld) with %d interrupts\n",
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bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
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tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG);
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tmp |= 1 << 1; /* soft reset */
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omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
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while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
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/* Wait for reset to complete */;
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}
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void __init omap_init_irq(void)
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{
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unsigned long nr_irqs = 0;
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unsigned int nr_banks = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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struct omap_irq_bank *bank = irq_banks + i;
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/* XXX */
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if (!bank->base_reg)
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continue;
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omap_irq_bank_init_one(bank);
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nr_irqs += bank->nr_irqs;
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nr_banks++;
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}
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printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
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nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
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for (i = 0; i < nr_irqs; i++) {
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set_irq_chip(i, &omap_irq_chip);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID);
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}
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}
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