775a0eca33
- Ensure that that last level cache ID is set in all cases, in the AMD CPU topology parsing code, in order to prevent invalid scheduling domain CPU masks -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmZAcSIACgkQEsHwGGHe VUr2Ww//Y+tY5iNLOCWCdD+nYcpGupletEUulvMLfEH42AZBNIHRyGCskuLWJAsw xBceY5uiTIAhKoSGUlbwIC+SWAdZQjxoF73KJQ55DQSOf7ogPW0SrQrvgI6QyTwb kRUNK+SQwqAVJBerFqz7gq9OhA6z+eewCDZPtcinIzWVC1zCVE0G4yEjAofDRF0F SbvS60fhFJCkQ/qi8Cz84tsO/+gTnYl3qyYPMCYkNtna5TyGv12tbDlSWSsATFBf 0WdlXjRmuC1xLkTm/CQeCWrVG0yfvcPzL6lYkTgx9tGI1UBuifn9LZFy82+j8V1+ tvAM3t7KC5pKa6xEok2L0+PflFsenaBEGoRZ1Os9nQvzCmnvTvLtEVn6DYrYykR4 HRrH/TLWTSPxWUNSj4d6HPd0meAIqFZtvFPp2/ublr+VNNk3kYVXGVYEHFgnbJhY EIAj1H3tDfCToMZ7FjS8wJpaiX5LAw75/onK4IUhoQZdHsqzIxvfjhzvjepctHV2 co5RFyY+W1K52AwZt4MHPNI4PUvNBcK9cqihDUZ3P5bKh7qWomTq/yrLuQSbuAhq /ImZgVPfmM9HKWQOyfr/6MmVQuis8TxYWL8mbQApoHEKpJOjlK9OziFnndQVV+Jh mSEIh8tcvUt0jKA2DfgiH6glkeBQOx5iaISeaMHOXIWPC/aW9vs= =y9je -----END PGP SIGNATURE----- Merge tag 'x86_urgent_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - Add a new PCI ID which belongs to a new AMD CPU family 0x1a - Ensure that that last level cache ID is set in all cases, in the AMD CPU topology parsing code, in order to prevent invalid scheduling domain CPU masks * tag 'x86_urgent_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/topology/amd: Ensure that LLC ID is initialized x86/amd_nb: Add new PCI IDs for AMD family 0x1a |
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acpi | ||
asm-generic | ||
clocksource | ||
crypto | ||
drm | ||
dt-bindings | ||
keys | ||
kunit | ||
kvm | ||
linux | ||
math-emu | ||
media | ||
memory | ||
misc | ||
net | ||
pcmcia | ||
ras | ||
rdma | ||
rv | ||
scsi | ||
soc | ||
sound | ||
target | ||
trace | ||
uapi | ||
ufs | ||
vdso | ||
video | ||
xen |