379 lines
11 KiB
C
379 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2023 Realtek Corporation
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*/
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#include "chan.h"
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#include "debug.h"
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#include "mac.h"
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#include "phy.h"
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#include "reg.h"
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#include "rtw8922a.h"
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#include "rtw8922a_rfk.h"
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static void rtw8922a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
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enum rtw89_rf_path path)
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{
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static const u32 tssi_trk_man[2] = {R_TSSI_PWR_P0, R_TSSI_PWR_P1};
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if (en)
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rtw89_phy_write32_mask(rtwdev, tssi_trk_man[path], B_TSSI_CONT_EN, 0);
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else
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rtw89_phy_write32_mask(rtwdev, tssi_trk_man[path], B_TSSI_CONT_EN, 1);
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}
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void rtw8922a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
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{
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if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
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if (phy_idx == RTW89_PHY_0)
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rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_A);
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else
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rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_B);
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} else {
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rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_A);
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rtw8922a_tssi_cont_en(rtwdev, en, RF_PATH_B);
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}
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}
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static
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void rtw8922a_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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u8 central_ch, enum rtw89_band band,
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enum rtw89_bandwidth bw)
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{
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const u32 rf_addr[2] = {RR_CFGCH, RR_CFGCH_V1};
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struct rtw89_hal *hal = &rtwdev->hal;
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u32 rf_reg[RF_PATH_NUM_8922A][2];
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u8 synpath;
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u32 rf18;
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u8 kpath;
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u8 path;
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u8 i;
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rf_reg[RF_PATH_A][0] = rtw89_read_rf(rtwdev, RF_PATH_A, rf_addr[0], RFREG_MASK);
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rf_reg[RF_PATH_A][1] = rtw89_read_rf(rtwdev, RF_PATH_A, rf_addr[1], RFREG_MASK);
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rf_reg[RF_PATH_B][0] = rtw89_read_rf(rtwdev, RF_PATH_B, rf_addr[0], RFREG_MASK);
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rf_reg[RF_PATH_B][1] = rtw89_read_rf(rtwdev, RF_PATH_B, rf_addr[1], RFREG_MASK);
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kpath = rtw89_phy_get_kpath(rtwdev, phy);
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synpath = rtw89_phy_get_syn_sel(rtwdev, phy);
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rf18 = rtw89_read_rf(rtwdev, synpath, RR_CFGCH, RFREG_MASK);
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if (rf18 == INV_RF_DATA) {
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rtw89_warn(rtwdev, "[RFK] Invalid RF18 value\n");
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return;
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}
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for (path = 0; path < RF_PATH_NUM_8922A; path++) {
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if (!(kpath & BIT(path)))
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continue;
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for (i = 0; i < 2; i++) {
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if (rf_reg[path][i] == INV_RF_DATA) {
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rtw89_warn(rtwdev,
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"[RFK] Invalid RF_0x18 for Path-%d\n", path);
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return;
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}
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rf_reg[path][i] &= ~(RR_CFGCH_BAND1 | RR_CFGCH_BW |
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RR_CFGCH_BAND0 | RR_CFGCH_CH);
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rf_reg[path][i] |= u32_encode_bits(central_ch, RR_CFGCH_CH);
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if (band == RTW89_BAND_2G)
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rtw89_write_rf(rtwdev, path, RR_SMD, RR_VCO2, 0x0);
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else
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rtw89_write_rf(rtwdev, path, RR_SMD, RR_VCO2, 0x1);
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switch (band) {
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case RTW89_BAND_2G:
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default:
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break;
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case RTW89_BAND_5G:
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rf_reg[path][i] |=
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u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
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u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
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break;
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case RTW89_BAND_6G:
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rf_reg[path][i] |=
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u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
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u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
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break;
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}
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switch (bw) {
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case RTW89_CHANNEL_WIDTH_5:
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case RTW89_CHANNEL_WIDTH_10:
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case RTW89_CHANNEL_WIDTH_20:
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default:
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break;
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case RTW89_CHANNEL_WIDTH_40:
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rf_reg[path][i] |=
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u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
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break;
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case RTW89_CHANNEL_WIDTH_80:
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rf_reg[path][i] |=
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u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
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break;
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case RTW89_CHANNEL_WIDTH_160:
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rf_reg[path][i] |=
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u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
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break;
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case RTW89_CHANNEL_WIDTH_320:
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rf_reg[path][i] |=
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u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
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break;
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}
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rtw89_write_rf(rtwdev, path, rf_addr[i],
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RFREG_MASK, rf_reg[path][i]);
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fsleep(100);
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}
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}
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if (hal->cv != CHIP_CAV)
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return;
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if (band == RTW89_BAND_2G) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x00003);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c990);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0xebe38);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000);
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} else {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x00003);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c190);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0xebe38);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000);
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}
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}
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void rtw8922a_set_channel_rf(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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rtw8922a_ctl_band_ch_bw(rtwdev, phy_idx, chan->channel, chan->band_type,
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chan->band_width);
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}
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enum _rf_syn_pow {
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RF_SYN_ON_OFF,
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RF_SYN_OFF_ON,
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RF_SYN_ALLON,
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RF_SYN_ALLOFF,
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};
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static void rtw8922a_set_syn01_cav(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
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{
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if (syn == RF_SYN_ALLON) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x2);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x2);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3);
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} else if (syn == RF_SYN_ON_OFF) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x2);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x0);
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} else if (syn == RF_SYN_OFF_ON) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x2);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x3);
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} else if (syn == RF_SYN_ALLOFF) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN, 0x0);
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}
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}
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static void rtw8922a_set_syn01_cbv(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
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{
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if (syn == RF_SYN_ALLON) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
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} else if (syn == RF_SYN_ON_OFF) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
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} else if (syn == RF_SYN_OFF_ON) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
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} else if (syn == RF_SYN_ALLOFF) {
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
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}
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}
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static void rtw8922a_set_syn01(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "SYN config=%d\n", syn);
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if (hal->cv == CHIP_CAV)
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rtw8922a_set_syn01_cav(rtwdev, syn);
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else
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rtw8922a_set_syn01_cbv(rtwdev, syn);
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}
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static void rtw8922a_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
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{
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u32 tmp;
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if (idx > 2) {
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rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx);
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return;
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}
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if (kpath & RF_A) {
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rtw89_phy_write32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_EN, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_IQC_V1, idx);
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rtw89_phy_write32_mask(rtwdev, R_COEF_SEL, B_COEF_SEL_MDPD_V1, idx);
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rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
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tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL, BIT(0));
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, tmp);
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tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL, BIT(1));
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G5, tmp);
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}
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if (kpath & RF_B) {
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rtw89_phy_write32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_EN, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_IQC_V1, idx);
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rtw89_phy_write32_mask(rtwdev, R_COEF_SEL_C1, B_COEF_SEL_MDPD_V1, idx);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
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tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL_C1, BIT(0));
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT_C1, B_CFIR_LUT_G3, tmp);
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tmp = rtw89_phy_read32_mask(rtwdev, R_COEF_SEL_C1, BIT(1));
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rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT_C1, B_CFIR_LUT_G5, tmp);
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}
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}
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static void rtw8922a_chlk_reload(struct rtw89_dev *rtwdev)
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{
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struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
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enum rtw89_sub_entity_idx sub_entity_idx;
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const struct rtw89_chan *chan;
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enum rtw89_entity_mode mode;
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u8 s0_tbl, s1_tbl;
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u8 tbl_sel;
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mode = rtw89_get_entity_mode(rtwdev);
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switch (mode) {
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case RTW89_ENTITY_MODE_MCC_PREPARE:
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sub_entity_idx = RTW89_SUB_ENTITY_1;
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tbl_sel = 1;
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break;
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default:
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sub_entity_idx = RTW89_SUB_ENTITY_0;
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tbl_sel = 0;
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break;
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}
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chan = rtw89_chan_get(rtwdev, sub_entity_idx);
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rfk_mcc->ch[tbl_sel] = chan->channel;
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rfk_mcc->band[tbl_sel] = chan->band_type;
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rfk_mcc->bw[tbl_sel] = chan->band_width;
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rfk_mcc->table_idx = tbl_sel;
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s0_tbl = tbl_sel;
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s1_tbl = tbl_sel;
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rtw8922a_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl);
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rtw8922a_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl);
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}
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static void rtw8922a_rfk_mlo_ctrl(struct rtw89_dev *rtwdev)
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{
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enum _rf_syn_pow syn_pow;
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if (!rtwdev->dbcc_en)
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goto set_rfk_reload;
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switch (rtwdev->mlo_dbcc_mode) {
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case MLO_0_PLUS_2_1RF:
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syn_pow = RF_SYN_OFF_ON;
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break;
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case MLO_0_PLUS_2_2RF:
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case MLO_1_PLUS_1_2RF:
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case MLO_2_PLUS_0_1RF:
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case MLO_2_PLUS_0_2RF:
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case MLO_2_PLUS_2_2RF:
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case MLO_DBCC_NOT_SUPPORT:
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default:
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syn_pow = RF_SYN_ON_OFF;
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break;
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case MLO_1_PLUS_1_1RF:
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case DBCC_LEGACY:
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syn_pow = RF_SYN_ALLON;
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break;
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}
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rtw8922a_set_syn01(rtwdev, syn_pow);
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set_rfk_reload:
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rtw8922a_chlk_reload(rtwdev);
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}
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static void rtw8922a_rfk_pll_init(struct rtw89_dev *rtwdev)
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{
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int ret;
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u8 tmp;
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ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_PLL_1, &tmp);
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if (ret)
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return;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, tmp | 0xf8, 0xFF);
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if (ret)
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return;
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ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_APBT, &tmp);
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if (ret)
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return;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_APBT, tmp & ~0x60, 0xFF);
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if (ret)
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return;
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ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_PLL, &tmp);
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if (ret)
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return;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_PLL, tmp | 0x38, 0xFF);
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if (ret)
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return;
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}
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void rtw8922a_rfk_hw_init(struct rtw89_dev *rtwdev)
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{
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if (rtwdev->dbcc_en)
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rtw8922a_rfk_mlo_ctrl(rtwdev);
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rtw8922a_rfk_pll_init(rtwdev);
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}
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void rtw8922a_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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{
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bool mlo_1_1;
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if (!rtwdev->dbcc_en)
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return;
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mlo_1_1 = rtw89_is_mlo_1_1(rtwdev);
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if (mlo_1_1)
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rtw8922a_set_syn01(rtwdev, RF_SYN_ALLON);
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else if (phy_idx == RTW89_PHY_0)
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rtw8922a_set_syn01(rtwdev, RF_SYN_ON_OFF);
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else
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rtw8922a_set_syn01(rtwdev, RF_SYN_OFF_ON);
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fsleep(1000);
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}
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void rtw8922a_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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{
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rtw8922a_rfk_mlo_ctrl(rtwdev);
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}
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