563 lines
15 KiB
C
563 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2023 Realtek Corporation
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*/
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#include "debug.h"
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#include "efuse.h"
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#include "mac.h"
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#include "reg.h"
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#define EFUSE_EXTERNALPN_ADDR_BE 0x1580
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#define EFUSE_B1_MSSDEVTYPE_MASK GENMASK(3, 0)
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#define EFUSE_B1_MSSCUSTIDX0_MASK GENMASK(7, 4)
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#define EFUSE_SERIALNUM_ADDR_BE 0x1581
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#define EFUSE_B2_MSSKEYNUM_MASK GENMASK(3, 0)
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#define EFUSE_B2_MSSCUSTIDX1_MASK BIT(6)
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#define EFUSE_SB_CRYP_SEL_ADDR 0x1582
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#define EFUSE_SB_CRYP_SEL_SIZE 2
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#define EFUSE_SB_CRYP_SEL_DEFAULT 0xFFFF
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#define SB_SEL_MGN_MAX_SIZE 2
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#define EFUSE_SEC_BE_START 0x1580
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#define EFUSE_SEC_BE_SIZE 4
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enum rtw89_efuse_mss_dev_type {
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MSS_DEV_TYPE_FWSEC_DEF = 0xF,
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MSS_DEV_TYPE_FWSEC_WINLIN_INBOX = 0xC,
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MSS_DEV_TYPE_FWSEC_NONLIN_INBOX_NON_COB = 0xA,
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MSS_DEV_TYPE_FWSEC_NONLIN_INBOX_COB = 0x9,
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MSS_DEV_TYPE_FWSEC_NONWIN_INBOX = 0x6,
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};
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static const u32 sb_sel_mgn[SB_SEL_MGN_MAX_SIZE] = {
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0x8000100, 0xC000180
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};
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static void rtw89_enable_efuse_pwr_cut_ddv_be(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_hal *hal = &rtwdev->hal;
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bool aphy_patch = true;
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if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV)
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aphy_patch = false;
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rtw89_write8_set(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
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if (aphy_patch) {
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rtw89_write16_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
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mdelay(1);
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rtw89_write16_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
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rtw89_write16_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
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}
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rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_EF_BURST);
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}
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static void rtw89_disable_efuse_pwr_cut_ddv_be(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_hal *hal = &rtwdev->hal;
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bool aphy_patch = true;
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if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV)
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aphy_patch = false;
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if (aphy_patch) {
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rtw89_write16_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
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rtw89_write16_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
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mdelay(1);
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rtw89_write16_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
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}
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rtw89_write8_clr(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
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rtw89_write32_clr(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_EF_BURST);
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}
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static int rtw89_dump_physical_efuse_map_ddv_be(struct rtw89_dev *rtwdev, u8 *map,
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u32 dump_addr, u32 dump_size)
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{
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u32 efuse_ctl;
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u32 addr;
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u32 data;
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int ret;
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if (!IS_ALIGNED(dump_addr, 4) || !IS_ALIGNED(dump_size, 4)) {
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rtw89_err(rtwdev, "Efuse addr 0x%x or size 0x%x not aligned\n",
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dump_addr, dump_size);
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return -EINVAL;
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}
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rtw89_enable_efuse_pwr_cut_ddv_be(rtwdev);
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for (addr = dump_addr; addr < dump_addr + dump_size; addr += 4, map += 4) {
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efuse_ctl = u32_encode_bits(addr, B_BE_EF_ADDR_MASK);
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rtw89_write32(rtwdev, R_BE_EFUSE_CTRL, efuse_ctl & ~B_BE_EF_RDY);
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ret = read_poll_timeout_atomic(rtw89_read32, efuse_ctl,
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efuse_ctl & B_BE_EF_RDY, 1, 1000000,
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true, rtwdev, R_BE_EFUSE_CTRL);
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if (ret)
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return -EBUSY;
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data = rtw89_read32(rtwdev, R_BE_EFUSE_CTRL_1_V1);
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*((__le32 *)map) = cpu_to_le32(data);
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}
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rtw89_disable_efuse_pwr_cut_ddv_be(rtwdev);
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return 0;
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}
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static int rtw89_dump_physical_efuse_map_dav_be(struct rtw89_dev *rtwdev, u8 *map,
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u32 dump_addr, u32 dump_size)
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{
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u32 addr;
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u8 val8;
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int err;
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int ret;
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for (addr = dump_addr; addr < dump_addr + dump_size; addr++) {
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, 0x40,
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FULL_BIT_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_LOW_ADDR, addr & 0xff,
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XTAL_SI_LOW_ADDR_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, addr >> 8,
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XTAL_SI_HIGH_ADDR_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, 0,
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XTAL_SI_MODE_SEL_MASK);
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if (ret)
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return ret;
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ret = read_poll_timeout_atomic(rtw89_mac_read_xtal_si, err,
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!err && (val8 & XTAL_SI_RDY),
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1, 10000, false,
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rtwdev, XTAL_SI_CTRL, &val8);
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if (ret) {
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rtw89_warn(rtwdev, "failed to read dav efuse\n");
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return ret;
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}
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ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_READ_VAL, &val8);
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if (ret)
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return ret;
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*map++ = val8;
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}
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return 0;
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}
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int rtw89_cnv_efuse_state_be(struct rtw89_dev *rtwdev, bool idle)
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{
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u32 val;
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int ret = 0;
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if (idle) {
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rtw89_write32_set(rtwdev, R_BE_WL_BT_PWR_CTRL, B_BE_BT_DISN_EN);
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} else {
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rtw89_write32_clr(rtwdev, R_BE_WL_BT_PWR_CTRL, B_BE_BT_DISN_EN);
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ret = read_poll_timeout(rtw89_read32_mask, val,
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val == MAC_AX_SYS_ACT, 50, 5000,
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false, rtwdev, R_BE_IC_PWR_STATE,
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B_BE_WHOLE_SYS_PWR_STE_MASK);
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if (ret)
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rtw89_warn(rtwdev, "failed to convert efuse state\n");
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}
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return ret;
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}
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static int rtw89_dump_physical_efuse_map_be(struct rtw89_dev *rtwdev, u8 *map,
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u32 dump_addr, u32 dump_size, bool dav)
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{
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int ret;
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if (!map || dump_size == 0)
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return 0;
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rtw89_cnv_efuse_state_be(rtwdev, false);
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if (dav) {
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ret = rtw89_dump_physical_efuse_map_dav_be(rtwdev, map,
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dump_addr, dump_size);
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if (ret)
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return ret;
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rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "phy_map dav: ", map, dump_size);
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} else {
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ret = rtw89_dump_physical_efuse_map_ddv_be(rtwdev, map,
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dump_addr, dump_size);
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if (ret)
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return ret;
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rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "phy_map ddv: ", map, dump_size);
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}
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rtw89_cnv_efuse_state_be(rtwdev, true);
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return 0;
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}
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#define EFUSE_HDR_CONST_MASK GENMASK(23, 20)
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#define EFUSE_HDR_PAGE_MASK GENMASK(19, 17)
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#define EFUSE_HDR_OFFSET_MASK GENMASK(16, 4)
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#define EFUSE_HDR_OFFSET_DAV_MASK GENMASK(11, 4)
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#define EFUSE_HDR_WORD_EN_MASK GENMASK(3, 0)
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#define invalid_efuse_header_be(hdr1, hdr2, hdr3) \
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((hdr1) == 0xff || (hdr2) == 0xff || (hdr3) == 0xff)
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#define invalid_efuse_content_be(word_en, i) \
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(((word_en) & BIT(i)) != 0x0)
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#define get_efuse_blk_idx_be(hdr1, hdr2, hdr3) \
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(((hdr1) << 16) | ((hdr2) << 8) | (hdr3))
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#define block_idx_to_logical_idx_be(blk_idx, i) \
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(((blk_idx) << 3) + ((i) << 1))
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#define invalid_efuse_header_dav_be(hdr1, hdr2) \
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((hdr1) == 0xff || (hdr2) == 0xff)
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#define get_efuse_blk_idx_dav_be(hdr1, hdr2) \
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(((hdr1) << 8) | (hdr2))
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static int rtw89_eeprom_parser_be(struct rtw89_dev *rtwdev,
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const u8 *phy_map, u32 phy_size, u8 *log_map,
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const struct rtw89_efuse_block_cfg *efuse_block)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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enum rtw89_efuse_block blk_page, page;
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u32 size = efuse_block->size;
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u32 phy_idx, log_idx;
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u32 hdr, page_offset;
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u8 hdr1, hdr2, hdr3;
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u8 i, val0, val1;
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u32 min, max;
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u16 blk_idx;
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u8 word_en;
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page = u32_get_bits(efuse_block->offset, RTW89_EFUSE_BLOCK_ID_MASK);
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page_offset = u32_get_bits(efuse_block->offset, RTW89_EFUSE_BLOCK_SIZE_MASK);
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min = ALIGN_DOWN(page_offset, 2);
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max = ALIGN(page_offset + size, 2);
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memset(log_map, 0xff, size);
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phy_idx = chip->sec_ctrl_efuse_size;
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do {
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if (page == RTW89_EFUSE_BLOCK_ADIE) {
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hdr1 = phy_map[phy_idx];
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hdr2 = phy_map[phy_idx + 1];
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if (invalid_efuse_header_dav_be(hdr1, hdr2))
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break;
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phy_idx += 2;
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hdr = get_efuse_blk_idx_dav_be(hdr1, hdr2);
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blk_page = RTW89_EFUSE_BLOCK_ADIE;
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blk_idx = u32_get_bits(hdr, EFUSE_HDR_OFFSET_DAV_MASK);
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word_en = u32_get_bits(hdr, EFUSE_HDR_WORD_EN_MASK);
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} else {
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hdr1 = phy_map[phy_idx];
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hdr2 = phy_map[phy_idx + 1];
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hdr3 = phy_map[phy_idx + 2];
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if (invalid_efuse_header_be(hdr1, hdr2, hdr3))
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break;
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phy_idx += 3;
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hdr = get_efuse_blk_idx_be(hdr1, hdr2, hdr3);
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blk_page = u32_get_bits(hdr, EFUSE_HDR_PAGE_MASK);
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blk_idx = u32_get_bits(hdr, EFUSE_HDR_OFFSET_MASK);
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word_en = u32_get_bits(hdr, EFUSE_HDR_WORD_EN_MASK);
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}
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if (blk_idx >= RTW89_EFUSE_MAX_BLOCK_SIZE >> 3) {
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rtw89_err(rtwdev, "[ERR]efuse idx:0x%X\n", phy_idx - 3);
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rtw89_err(rtwdev, "[ERR]read hdr:0x%X\n", hdr);
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return -EINVAL;
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}
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for (i = 0; i < 4; i++) {
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if (invalid_efuse_content_be(word_en, i))
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continue;
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if (phy_idx >= phy_size - 1)
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return -EINVAL;
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log_idx = block_idx_to_logical_idx_be(blk_idx, i);
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if (blk_page == page && log_idx >= min && log_idx < max) {
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val0 = phy_map[phy_idx];
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val1 = phy_map[phy_idx + 1];
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if (log_idx == min && page_offset > min) {
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log_map[log_idx - page_offset + 1] = val1;
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} else if (log_idx + 2 == max &&
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page_offset + size < max) {
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log_map[log_idx - page_offset] = val0;
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} else {
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log_map[log_idx - page_offset] = val0;
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log_map[log_idx - page_offset + 1] = val1;
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}
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}
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phy_idx += 2;
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}
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} while (phy_idx < phy_size);
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return 0;
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}
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static int rtw89_parse_logical_efuse_block_be(struct rtw89_dev *rtwdev,
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const u8 *phy_map, u32 phy_size,
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enum rtw89_efuse_block block)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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const struct rtw89_efuse_block_cfg *efuse_block;
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u8 *log_map;
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int ret;
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efuse_block = &chip->efuse_blocks[block];
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log_map = kmalloc(efuse_block->size, GFP_KERNEL);
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if (!log_map)
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return -ENOMEM;
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ret = rtw89_eeprom_parser_be(rtwdev, phy_map, phy_size, log_map, efuse_block);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse logical block %d\n", block);
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goto out_free;
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}
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rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "log_map: ", log_map, efuse_block->size);
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ret = rtwdev->chip->ops->read_efuse(rtwdev, log_map, block);
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if (ret) {
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rtw89_warn(rtwdev, "failed to read efuse map\n");
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goto out_free;
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}
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out_free:
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kfree(log_map);
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return ret;
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}
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int rtw89_parse_efuse_map_be(struct rtw89_dev *rtwdev)
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{
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u32 phy_size = rtwdev->chip->physical_efuse_size;
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u32 dav_phy_size = rtwdev->chip->dav_phy_efuse_size;
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enum rtw89_efuse_block block;
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u8 *phy_map = NULL;
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u8 *dav_phy_map = NULL;
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int ret;
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if (rtw89_read16(rtwdev, R_BE_SYS_WL_EFUSE_CTRL) & B_BE_AUTOLOAD_SUS)
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rtwdev->efuse.valid = true;
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else
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rtw89_warn(rtwdev, "failed to check efuse autoload\n");
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phy_map = kmalloc(phy_size, GFP_KERNEL);
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if (dav_phy_size)
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dav_phy_map = kmalloc(dav_phy_size, GFP_KERNEL);
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if (!phy_map || (dav_phy_size && !dav_phy_map)) {
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ret = -ENOMEM;
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goto out_free;
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}
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ret = rtw89_dump_physical_efuse_map_be(rtwdev, phy_map, 0, phy_size, false);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse physical map\n");
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goto out_free;
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}
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ret = rtw89_dump_physical_efuse_map_be(rtwdev, dav_phy_map, 0, dav_phy_size, true);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump efuse dav physical map\n");
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goto out_free;
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}
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if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
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block = RTW89_EFUSE_BLOCK_HCI_DIG_USB;
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else
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block = RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO;
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ret = rtw89_parse_logical_efuse_block_be(rtwdev, phy_map, phy_size, block);
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if (ret) {
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rtw89_warn(rtwdev, "failed to parse efuse logic block %d\n",
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RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO);
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goto out_free;
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}
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ret = rtw89_parse_logical_efuse_block_be(rtwdev, phy_map, phy_size,
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RTW89_EFUSE_BLOCK_RF);
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if (ret) {
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rtw89_warn(rtwdev, "failed to parse efuse logic block %d\n",
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RTW89_EFUSE_BLOCK_RF);
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goto out_free;
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}
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out_free:
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kfree(dav_phy_map);
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kfree(phy_map);
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return ret;
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}
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int rtw89_parse_phycap_map_be(struct rtw89_dev *rtwdev)
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{
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u32 phycap_addr = rtwdev->chip->phycap_addr;
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u32 phycap_size = rtwdev->chip->phycap_size;
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u8 *phycap_map = NULL;
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int ret = 0;
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if (!phycap_size)
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return 0;
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phycap_map = kmalloc(phycap_size, GFP_KERNEL);
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if (!phycap_map)
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return -ENOMEM;
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ret = rtw89_dump_physical_efuse_map_be(rtwdev, phycap_map,
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phycap_addr, phycap_size, false);
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if (ret) {
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rtw89_warn(rtwdev, "failed to dump phycap map\n");
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goto out_free;
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}
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ret = rtwdev->chip->ops->read_phycap(rtwdev, phycap_map);
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if (ret) {
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rtw89_warn(rtwdev, "failed to read phycap map\n");
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goto out_free;
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}
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out_free:
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kfree(phycap_map);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u16 get_sb_cryp_sel_idx(u16 sb_cryp_sel)
|
|
{
|
|
u8 low_bit, high_bit, cnt_zero = 0;
|
|
u8 idx, sel_form_v, sel_idx_v;
|
|
u16 sb_cryp_sel_v = 0x0;
|
|
|
|
sel_form_v = u16_get_bits(sb_cryp_sel, MASKBYTE0);
|
|
sel_idx_v = u16_get_bits(sb_cryp_sel, MASKBYTE1);
|
|
|
|
for (idx = 0; idx < 4; idx++) {
|
|
low_bit = !!(sel_form_v & BIT(idx));
|
|
high_bit = !!(sel_form_v & BIT(7 - idx));
|
|
if (low_bit != high_bit)
|
|
return U16_MAX;
|
|
if (low_bit)
|
|
continue;
|
|
|
|
cnt_zero++;
|
|
if (cnt_zero == 1)
|
|
sb_cryp_sel_v = idx * 16;
|
|
else if (cnt_zero > 1)
|
|
return U16_MAX;
|
|
}
|
|
|
|
low_bit = u8_get_bits(sel_idx_v, 0x0F);
|
|
high_bit = u8_get_bits(sel_idx_v, 0xF0);
|
|
|
|
if ((low_bit ^ high_bit) != 0xF)
|
|
return U16_MAX;
|
|
|
|
return sb_cryp_sel_v + low_bit;
|
|
}
|
|
|
|
static u8 get_mss_dev_type_idx(struct rtw89_dev *rtwdev, u8 mss_dev_type)
|
|
{
|
|
switch (mss_dev_type) {
|
|
case MSS_DEV_TYPE_FWSEC_WINLIN_INBOX:
|
|
mss_dev_type = 0x0;
|
|
break;
|
|
case MSS_DEV_TYPE_FWSEC_NONLIN_INBOX_NON_COB:
|
|
mss_dev_type = 0x1;
|
|
break;
|
|
case MSS_DEV_TYPE_FWSEC_NONLIN_INBOX_COB:
|
|
mss_dev_type = 0x2;
|
|
break;
|
|
case MSS_DEV_TYPE_FWSEC_NONWIN_INBOX:
|
|
mss_dev_type = 0x3;
|
|
break;
|
|
case MSS_DEV_TYPE_FWSEC_DEF:
|
|
mss_dev_type = RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF;
|
|
break;
|
|
default:
|
|
rtw89_warn(rtwdev, "unknown mss_dev_type %d", mss_dev_type);
|
|
mss_dev_type = RTW89_FW_MSS_DEV_TYPE_FWSEC_INV;
|
|
break;
|
|
}
|
|
|
|
return mss_dev_type;
|
|
}
|
|
|
|
int rtw89_efuse_read_fw_secure_be(struct rtw89_dev *rtwdev)
|
|
{
|
|
struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
|
|
u32 sec_addr = EFUSE_SEC_BE_START;
|
|
u32 sec_size = EFUSE_SEC_BE_SIZE;
|
|
u16 sb_cryp_sel, sb_cryp_sel_idx;
|
|
u8 sec_map[EFUSE_SEC_BE_SIZE];
|
|
u8 mss_dev_type;
|
|
u8 b1, b2;
|
|
int ret;
|
|
|
|
ret = rtw89_dump_physical_efuse_map_be(rtwdev, sec_map,
|
|
sec_addr, sec_size, false);
|
|
if (ret) {
|
|
rtw89_warn(rtwdev, "failed to dump secsel map\n");
|
|
return ret;
|
|
}
|
|
|
|
sb_cryp_sel = sec_map[EFUSE_SB_CRYP_SEL_ADDR - sec_addr] |
|
|
sec_map[EFUSE_SB_CRYP_SEL_ADDR - sec_addr + 1] << 8;
|
|
if (sb_cryp_sel == EFUSE_SB_CRYP_SEL_DEFAULT)
|
|
goto out;
|
|
|
|
sb_cryp_sel_idx = get_sb_cryp_sel_idx(sb_cryp_sel);
|
|
if (sb_cryp_sel_idx >= SB_SEL_MGN_MAX_SIZE) {
|
|
rtw89_warn(rtwdev, "invalid SB cryp sel idx %d\n", sb_cryp_sel_idx);
|
|
goto out;
|
|
}
|
|
|
|
sec->sb_sel_mgn = sb_sel_mgn[sb_cryp_sel_idx];
|
|
|
|
b1 = sec_map[EFUSE_EXTERNALPN_ADDR_BE - sec_addr];
|
|
b2 = sec_map[EFUSE_SERIALNUM_ADDR_BE - sec_addr];
|
|
|
|
mss_dev_type = u8_get_bits(b1, EFUSE_B1_MSSDEVTYPE_MASK);
|
|
sec->mss_cust_idx = 0x1F - (u8_get_bits(b1, EFUSE_B1_MSSCUSTIDX0_MASK) |
|
|
u8_get_bits(b2, EFUSE_B2_MSSCUSTIDX1_MASK) << 4);
|
|
sec->mss_key_num = 0xF - u8_get_bits(b2, EFUSE_B2_MSSKEYNUM_MASK);
|
|
|
|
sec->mss_dev_type = get_mss_dev_type_idx(rtwdev, mss_dev_type);
|
|
if (sec->mss_dev_type == RTW89_FW_MSS_DEV_TYPE_FWSEC_INV) {
|
|
rtw89_warn(rtwdev, "invalid mss_dev_type %d\n", mss_dev_type);
|
|
goto out;
|
|
}
|
|
|
|
sec->secure_boot = true;
|
|
|
|
out:
|
|
rtw89_debug(rtwdev, RTW89_DBG_FW,
|
|
"MSS secure_boot=%d dev_type=%d cust_idx=%d key_num=%d\n",
|
|
sec->secure_boot, sec->mss_dev_type, sec->mss_cust_idx,
|
|
sec->mss_key_num);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(rtw89_efuse_read_fw_secure_be);
|