133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Technologic Systems TS-73xx SBC FPGA loader
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*
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* Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
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*
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* FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
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* TS-7300, heavily based on load_fpga.c in their vendor tree.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <linux/iopoll.h>
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#include <linux/fpga/fpga-mgr.h>
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#define TS73XX_FPGA_DATA_REG 0
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#define TS73XX_FPGA_CONFIG_REG 1
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#define TS73XX_FPGA_WRITE_DONE 0x1
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#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
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#define TS73XX_FPGA_RESET 0x2
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#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
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#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
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#define TS73XX_FPGA_LOAD_OK 0x4
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#define TS73XX_FPGA_CONFIG_LOAD 0x8
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struct ts73xx_fpga_priv {
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void __iomem *io_base;
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struct device *dev;
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};
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static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct ts73xx_fpga_priv *priv = mgr->priv;
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/* Reset the FPGA */
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writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
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udelay(TS73XX_FPGA_RESET_LOW_DELAY);
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writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
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udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
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return 0;
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}
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static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct ts73xx_fpga_priv *priv = mgr->priv;
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size_t i = 0;
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int ret;
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u8 reg;
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while (count--) {
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ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
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reg, !(reg & TS73XX_FPGA_WRITE_DONE),
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1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
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if (ret < 0)
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return ret;
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writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
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i++;
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}
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return 0;
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}
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static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct ts73xx_fpga_priv *priv = mgr->priv;
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u8 reg;
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usleep_range(1000, 2000);
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reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
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reg |= TS73XX_FPGA_CONFIG_LOAD;
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writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
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usleep_range(1000, 2000);
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reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
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reg &= ~TS73XX_FPGA_CONFIG_LOAD;
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writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
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reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
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if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
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return -ETIMEDOUT;
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return 0;
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}
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static const struct fpga_manager_ops ts73xx_fpga_ops = {
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.write_init = ts73xx_fpga_write_init,
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.write = ts73xx_fpga_write,
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.write_complete = ts73xx_fpga_write_complete,
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};
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static int ts73xx_fpga_probe(struct platform_device *pdev)
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{
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struct device *kdev = &pdev->dev;
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struct ts73xx_fpga_priv *priv;
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struct fpga_manager *mgr;
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priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = kdev;
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priv->io_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->io_base))
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return PTR_ERR(priv->io_base);
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mgr = devm_fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
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&ts73xx_fpga_ops, priv);
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return PTR_ERR_OR_ZERO(mgr);
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}
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static struct platform_driver ts73xx_fpga_driver = {
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.driver = {
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.name = "ts73xx-fpga-mgr",
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},
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.probe = ts73xx_fpga_probe,
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};
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module_platform_driver(ts73xx_fpga_driver);
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MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
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MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
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MODULE_LICENSE("GPL v2");
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