304 lines
7.8 KiB
C
304 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Clock driver for Loongson-1 SoC
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*
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* Copyright (C) 2012-2023 Keguang Zhang <keguang.zhang@gmail.com>
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*/
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/container_of.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/printk.h>
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#include <dt-bindings/clock/loongson,ls1x-clk.h>
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/* Loongson 1 Clock Register Definitions */
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#define CLK_PLL_FREQ 0x0
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#define CLK_PLL_DIV 0x4
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static DEFINE_SPINLOCK(ls1x_clk_div_lock);
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struct ls1x_clk_pll_data {
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u32 fixed;
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u8 shift;
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u8 int_shift;
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u8 int_width;
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u8 frac_shift;
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u8 frac_width;
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};
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struct ls1x_clk_div_data {
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u8 shift;
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u8 width;
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unsigned long flags;
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const struct clk_div_table *table;
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u8 bypass_shift;
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u8 bypass_inv;
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spinlock_t *lock; /* protect access to DIV registers */
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};
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struct ls1x_clk {
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void __iomem *reg;
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unsigned int offset;
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struct clk_hw hw;
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const void *data;
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};
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#define to_ls1x_clk(_hw) container_of(_hw, struct ls1x_clk, hw)
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static inline unsigned long ls1x_pll_rate_part(unsigned int val,
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unsigned int shift,
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unsigned int width)
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{
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return (val & GENMASK(shift + width, shift)) >> shift;
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}
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static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
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const struct ls1x_clk_pll_data *d = ls1x_clk->data;
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u32 val, rate;
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val = readl(ls1x_clk->reg);
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rate = d->fixed;
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rate += ls1x_pll_rate_part(val, d->int_shift, d->int_width);
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if (d->frac_width)
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rate += ls1x_pll_rate_part(val, d->frac_shift, d->frac_width);
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rate *= parent_rate;
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rate >>= d->shift;
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return rate;
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}
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static const struct clk_ops ls1x_pll_clk_ops = {
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.recalc_rate = ls1x_pll_recalc_rate,
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};
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static unsigned long ls1x_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
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const struct ls1x_clk_div_data *d = ls1x_clk->data;
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unsigned int val;
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val = readl(ls1x_clk->reg) >> d->shift;
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val &= clk_div_mask(d->width);
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return divider_recalc_rate(hw, parent_rate, val, d->table,
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d->flags, d->width);
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}
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static long ls1x_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
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const struct ls1x_clk_div_data *d = ls1x_clk->data;
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return divider_round_rate(hw, rate, prate, d->table,
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d->width, d->flags);
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}
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static int ls1x_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
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const struct ls1x_clk_div_data *d = ls1x_clk->data;
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int val, div_val;
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unsigned long flags = 0;
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div_val = divider_get_val(rate, parent_rate, d->table,
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d->width, d->flags);
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if (div_val < 0)
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return div_val;
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spin_lock_irqsave(d->lock, flags);
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/* Bypass the clock */
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val = readl(ls1x_clk->reg);
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if (d->bypass_inv)
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val &= ~BIT(d->bypass_shift);
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else
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val |= BIT(d->bypass_shift);
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writel(val, ls1x_clk->reg);
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val = readl(ls1x_clk->reg);
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val &= ~(clk_div_mask(d->width) << d->shift);
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val |= (u32)div_val << d->shift;
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writel(val, ls1x_clk->reg);
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/* Restore the clock */
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val = readl(ls1x_clk->reg);
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if (d->bypass_inv)
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val |= BIT(d->bypass_shift);
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else
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val &= ~BIT(d->bypass_shift);
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writel(val, ls1x_clk->reg);
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spin_unlock_irqrestore(d->lock, flags);
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return 0;
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}
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static const struct clk_ops ls1x_clk_divider_ops = {
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.recalc_rate = ls1x_divider_recalc_rate,
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.round_rate = ls1x_divider_round_rate,
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.set_rate = ls1x_divider_set_rate,
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};
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#define LS1X_CLK_PLL(_name, _offset, _fixed, _shift, \
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f_shift, f_width, i_shift, i_width) \
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struct ls1x_clk _name = { \
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.offset = (_offset), \
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.data = &(const struct ls1x_clk_pll_data) { \
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.fixed = (_fixed), \
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.shift = (_shift), \
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.int_shift = (i_shift), \
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.int_width = (i_width), \
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.frac_shift = (f_shift), \
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.frac_width = (f_width), \
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}, \
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.hw.init = &(const struct clk_init_data) { \
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.name = #_name, \
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.ops = &ls1x_pll_clk_ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "xtal", \
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.name = "xtal", \
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.index = -1, \
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}, \
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.num_parents = 1, \
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}, \
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}
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#define LS1X_CLK_DIV(_name, _pname, _offset, _shift, _width, \
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_table, _bypass_shift, _bypass_inv, _flags) \
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struct ls1x_clk _name = { \
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.offset = (_offset), \
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.data = &(const struct ls1x_clk_div_data){ \
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.shift = (_shift), \
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.width = (_width), \
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.table = (_table), \
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.flags = (_flags), \
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.bypass_shift = (_bypass_shift), \
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.bypass_inv = (_bypass_inv), \
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.lock = &ls1x_clk_div_lock, \
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}, \
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.hw.init = &(const struct clk_init_data) { \
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.name = #_name, \
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.ops = &ls1x_clk_divider_ops, \
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.parent_hws = (const struct clk_hw *[]) { _pname }, \
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.num_parents = 1, \
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.flags = CLK_GET_RATE_NOCACHE, \
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}, \
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}
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static LS1X_CLK_PLL(ls1b_clk_pll, CLK_PLL_FREQ, 12, 1, 0, 5, 0, 0);
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static LS1X_CLK_DIV(ls1b_clk_cpu, &ls1b_clk_pll.hw, CLK_PLL_DIV,
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20, 4, NULL, 8, 0,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST);
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static LS1X_CLK_DIV(ls1b_clk_dc, &ls1b_clk_pll.hw, CLK_PLL_DIV,
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26, 4, NULL, 12, 0, CLK_DIVIDER_ONE_BASED);
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static LS1X_CLK_DIV(ls1b_clk_ahb, &ls1b_clk_pll.hw, CLK_PLL_DIV,
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14, 4, NULL, 10, 0, CLK_DIVIDER_ONE_BASED);
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static CLK_FIXED_FACTOR(ls1b_clk_apb, "ls1b_clk_apb", "ls1b_clk_ahb", 2, 1,
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CLK_SET_RATE_PARENT);
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static struct clk_hw_onecell_data ls1b_clk_hw_data = {
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.hws = {
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[LS1X_CLKID_PLL] = &ls1b_clk_pll.hw,
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[LS1X_CLKID_CPU] = &ls1b_clk_cpu.hw,
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[LS1X_CLKID_DC] = &ls1b_clk_dc.hw,
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[LS1X_CLKID_AHB] = &ls1b_clk_ahb.hw,
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[LS1X_CLKID_APB] = &ls1b_clk_apb.hw,
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},
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.num = CLK_NR_CLKS,
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};
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static const struct clk_div_table ls1c_ahb_div_table[] = {
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[0] = { .val = 0, .div = 2 },
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[1] = { .val = 1, .div = 4 },
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[2] = { .val = 2, .div = 3 },
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[3] = { .val = 3, .div = 3 },
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[4] = { /* sentinel */ }
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};
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static LS1X_CLK_PLL(ls1c_clk_pll, CLK_PLL_FREQ, 0, 2, 8, 8, 16, 8);
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static LS1X_CLK_DIV(ls1c_clk_cpu, &ls1c_clk_pll.hw, CLK_PLL_DIV,
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8, 7, NULL, 0, 1,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST);
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static LS1X_CLK_DIV(ls1c_clk_dc, &ls1c_clk_pll.hw, CLK_PLL_DIV,
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24, 7, NULL, 4, 1, CLK_DIVIDER_ONE_BASED);
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static LS1X_CLK_DIV(ls1c_clk_ahb, &ls1c_clk_cpu.hw, CLK_PLL_FREQ,
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0, 2, ls1c_ahb_div_table, 0, 0, CLK_DIVIDER_ALLOW_ZERO);
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static CLK_FIXED_FACTOR(ls1c_clk_apb, "ls1c_clk_apb", "ls1c_clk_ahb", 1, 1,
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CLK_SET_RATE_PARENT);
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static struct clk_hw_onecell_data ls1c_clk_hw_data = {
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.hws = {
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[LS1X_CLKID_PLL] = &ls1c_clk_pll.hw,
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[LS1X_CLKID_CPU] = &ls1c_clk_cpu.hw,
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[LS1X_CLKID_DC] = &ls1c_clk_dc.hw,
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[LS1X_CLKID_AHB] = &ls1c_clk_ahb.hw,
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[LS1X_CLKID_APB] = &ls1c_clk_apb.hw,
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},
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.num = CLK_NR_CLKS,
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};
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static void __init ls1x_clk_init(struct device_node *np,
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struct clk_hw_onecell_data *hw_data)
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{
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struct ls1x_clk *ls1x_clk;
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void __iomem *reg;
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int i, ret;
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reg = of_iomap(np, 0);
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if (!reg) {
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pr_err("Unable to map base for %pOF\n", np);
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return;
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}
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for (i = 0; i < hw_data->num; i++) {
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/* array might be sparse */
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if (!hw_data->hws[i])
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continue;
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if (i != LS1X_CLKID_APB) {
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ls1x_clk = to_ls1x_clk(hw_data->hws[i]);
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ls1x_clk->reg = reg + ls1x_clk->offset;
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}
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ret = of_clk_hw_register(np, hw_data->hws[i]);
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if (ret)
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goto err;
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}
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_data);
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if (!ret)
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return;
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err:
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pr_err("Failed to register %pOF\n", np);
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while (--i >= 0)
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clk_hw_unregister(hw_data->hws[i]);
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iounmap(reg);
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}
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static void __init ls1b_clk_init(struct device_node *np)
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{
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return ls1x_clk_init(np, &ls1b_clk_hw_data);
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}
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static void __init ls1c_clk_init(struct device_node *np)
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{
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return ls1x_clk_init(np, &ls1c_clk_hw_data);
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}
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CLK_OF_DECLARE(ls1b_clk, "loongson,ls1b-clk", ls1b_clk_init);
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CLK_OF_DECLARE(ls1c_clk, "loongson,ls1c-clk", ls1c_clk_init);
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