wifi: rtw89: wow: update config mac function with different generation
The registers to configure mac function for WoWLAN mode that are different from different generation, so update them. Signed-off-by: Chin-Yen Lee <timlee@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240302005828.13666-5-pkshih@realtek.com
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@ -64,6 +64,8 @@ struct rtw89_h2creg_sch_tx_en {
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#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
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#define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
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#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
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#define RTW89_H2CREG_MAX 4
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#define RTW89_C2HREG_MAX 4
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#define RTW89_C2HREG_HDR_LEN 2
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@ -95,7 +97,9 @@ enum rtw89_mac_h2c_type {
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RTW89_FWCMD_H2CREG_FUNC_FWERR,
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RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
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RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
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RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
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RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
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RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP = 0x6,
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RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL = 0xA,
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};
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enum rtw89_mac_c2h_type {
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@ -104,7 +108,8 @@ enum rtw89_mac_c2h_type {
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RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
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RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
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RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
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RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
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RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
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RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
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};
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enum rtw89_fw_c2h_category {
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@ -6266,6 +6266,41 @@ int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
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return ret;
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}
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static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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int ret;
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if (enable_wow) {
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ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true);
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if (ret) {
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rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
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return ret;
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}
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rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
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rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
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rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
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rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
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rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
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rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
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rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
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} else {
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ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
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if (ret) {
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rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
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return ret;
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}
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rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
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rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
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rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
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rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
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}
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return 0;
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}
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static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
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{
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u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL);
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@ -6357,5 +6392,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
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.add_chan_list = rtw89_hw_scan_add_chan_list,
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.scan_offload = rtw89_fw_h2c_scan_offload,
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.wow_config_mac = rtw89_wow_config_mac_ax,
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};
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EXPORT_SYMBOL(rtw89_mac_gen_ax);
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@ -169,6 +169,12 @@ enum rtw89_mac_ax_l0_to_l1_event {
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MAC_AX_L0_TO_L1_EVENT_MAX = 15,
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};
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enum rtw89_mac_wow_fw_status {
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WOWLAN_NOT_READY = 0x00,
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WOWLAN_SLEEP_READY = 0x01,
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WOWLAN_RESUME_READY = 0x02,
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};
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#define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
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enum rtw89_mac_dbg_port_sel {
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@ -980,6 +986,8 @@ struct rtw89_mac_gen_def {
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int (*scan_offload)(struct rtw89_dev *rtwdev,
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struct rtw89_scan_option *option,
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struct rtw89_vif *rtwvif);
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int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
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};
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extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
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@ -2307,6 +2307,52 @@ static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev)
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dump_err_status_dispatcher_be(rtwdev);
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}
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static int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
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{
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struct rtw89_mac_h2c_info h2c_info = {};
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struct rtw89_mac_c2h_info c2h_info = {};
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u32 ret;
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h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL;
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h2c_info.content_len = sizeof(h2c_info.u.hdr);
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h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN);
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ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
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if (ret)
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return ret;
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if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK)
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ret = -EINVAL;
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return ret;
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}
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static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow)
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{
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if (enable_wow) {
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rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
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rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE);
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rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
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rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
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rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
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rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0);
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rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0);
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rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0);
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rtw89_write32(rtwdev, R_BE_FWD_TF0, 0);
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rtw89_write32(rtwdev, R_BE_FWD_TF1, 0);
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rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
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rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0);
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rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
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} else {
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rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
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rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
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rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT);
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rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
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}
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return 0;
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}
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static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev,
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u8 band)
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{
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@ -2569,5 +2615,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
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.add_chan_list = rtw89_hw_scan_add_chan_list_be,
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.scan_offload = rtw89_fw_h2c_scan_offload_be,
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.wow_config_mac = rtw89_wow_config_mac_be,
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};
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EXPORT_SYMBOL(rtw89_mac_gen_be);
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@ -4456,6 +4456,9 @@
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#define B_BE_HCI_RXDMA_EN BIT(1)
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#define B_BE_HCI_TXDMA_EN BIT(0)
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#define R_BE_DBG_WOW_READY 0x815E
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#define B_BE_DBG_WOW_READY GENMASK(7, 0)
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#define R_BE_DMAC_FUNC_EN 0x8400
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#define B_BE_DMAC_CRPRT BIT(31)
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#define B_BE_MAC_FUNC_EN BIT(30)
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@ -5009,6 +5012,12 @@
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B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
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B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN)
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#define R_BE_RX_STOP 0x8914
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#define B_BE_CPU_RX_STOP BIT(17)
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#define B_BE_HOST_RX_STOP BIT(16)
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#define B_BE_CPU_RX_CH_STOP_MSK GENMASK(15, 8)
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#define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0)
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#define R_BE_DISP_FWD_WLAN_0 0x8938
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#define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30)
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#define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28)
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@ -5524,6 +5533,13 @@
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#define B_BE_DROP_NONDMA_PPDU BIT(2)
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#define B_BE_APPEND_FCS BIT(0)
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#define R_BE_FWD_ERR 0x9C10
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#define R_BE_FWD_ACTN0 0x9C14
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#define R_BE_FWD_ACTN1 0x9C18
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#define R_BE_FWD_ACTN2 0x9C1C
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#define R_BE_FWD_TF0 0x9C20
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#define R_BE_FWD_TF1 0x9C24
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#define R_BE_HW_PPDU_STATUS 0x9C30
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#define B_BE_FWD_RPKTTYPE_MASK GENMASK(31, 26)
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#define B_BE_FWD_PPDU_PRTID_MASK GENMASK(25, 23)
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@ -41,34 +41,8 @@ static void rtw89_wow_leave_lps(struct rtw89_dev *rtwdev)
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static int rtw89_wow_config_mac(struct rtw89_dev *rtwdev, bool enable_wow)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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int ret;
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if (enable_wow) {
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ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true);
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if (ret) {
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rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
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return ret;
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}
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rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
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rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
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rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
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rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
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rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
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rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
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rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
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} else {
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ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
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if (ret) {
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rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
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return ret;
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}
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rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
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rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
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rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
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rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
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}
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return 0;
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return mac->wow_config_mac(rtwdev, enable_wow);
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}
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static void rtw89_wow_set_rx_filter(struct rtw89_dev *rtwdev, bool enable)
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