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Pin control fixes for the v6.9 series: 

- Fix a double-free in the pinctrl_enable() errorpath.
 
 - Fix a refcount leak in pinctrl_dt_to_map().
 
 - Fix selecting the GPIO pin control state and the UART3
   pin config group in the Intel Baytrail driver.
 
 - Fix readback of schmitt trigger status in the Mediatek
   Paris driver, along with some semantic pin config issues
   in this driver.
 
 - Fix a pin suffix typo in the Meson A1 driver.
 
 - Fix an erroneous register offset in he Aspeed G6 driver.
 
 - Fix an inconsistent lock state and the interrupt type on
   resume in the Renesas RZG2L driver.
 
 - Fix some minor confusion in the Renesas DT bindings.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmYwnFsACgkQQRCzN7AZ
 XXNOgw/9HiN5N8Z869DT92OOQn8cFAshkxB/oN9ltd/Mzc73RquNB6pSAB1k43t1
 6TnhHhMQOswflGOTR9aSdo96iHwx596D1nyCy56uSX9dGa2I9smwIpBoeT1rNTmM
 HEt0CbHAWJ93F2BTBXNy6/fgLM/fZtD4SiCSiUynluUA9s/mSx7JmA6Lly6WSQBF
 cRLj4DbVEKOUaHLcB90G0NI8VtJzjaRIdTkSqawd0SVVz+8vBmdLNWib6XvUsEP7
 rQMs5omy+NSOWK0gKOUzXVZaXq8glbah3lZtFBZkZPjr13ymRjAipyhS0K3G6xhS
 9jCSYfkwnpO3xb/D9/ZYhDd2FC3bQmphxMIzb/LYWoNDp6mdyQxbGtnO5lco9fI1
 TcOfMpP24M6Eong9xiFUiIY/yghX10yBsbWzwX6qEO8O85DHmH0JWu8akHhKKPwJ
 7W1uWxAtC0URWSG3qEDpcUzB8shWK7T5jNjgvsDn/cUyQ7WXk1XjOa17U1Ka019R
 v+XvJ0Z0RHn2eqKme9OfX6W5zC0fD4P5nQpE6KW051U0/wSyQVGPTzcIJGa23JeF
 ZvS/2te2dsmCZtlg0lmwdzi10p3QmFZ4t1xbxVgXt2VMvD6zWRwtyP76O4Nwbwg2
 OaLQVVbinDZQ90e1FaYSWNNN8jTuUo781kEZiq6gEaJfnlblV5A=
 =BG4d
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - Fix a double-free in the pinctrl_enable() errorpath

 - Fix a refcount leak in pinctrl_dt_to_map()

 - Fix selecting the GPIO pin control state and the UART3 pin config
   group in the Intel Baytrail driver

 - Fix readback of schmitt trigger status in the Mediatek Paris driver,
   along with some semantic pin config issues in this driver

 - Fix a pin suffix typo in the Meson A1 driver

 - Fix an erroneous register offset in he Aspeed G6 driver

 - Fix an inconsistent lock state and the interrupt type on resume in
   the Renesas RZG2L driver

 - Fix some minor confusion in the Renesas DT bindings

* tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: renesas: rzg2l: Configure the interrupt type on resume
  pinctrl: devicetree: fix refcount leak in pinctrl_dt_to_map()
  pinctrl: baytrail: Add pinconf group for uart3
  pinctrl: baytrail: Fix selecting gpio pinctrl state
  pinctrl: mediatek: paris: Rework support for PIN_CONFIG_{INPUT,OUTPUT}_ENABLE
  pinctrl: mediatek: paris: Fix PIN_CONFIG_INPUT_SCHMITT_ENABLE readback
  pinctrl: core: delete incorrect free in pinctrl_enable()
  pinctrl/meson: fix typo in PDM's pin name
  pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T
  pinctrl: renesas: rzg2l: Execute atomically the interrupt configuration
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties
This commit is contained in:
Linus Torvalds 2024-04-30 08:50:58 -07:00
parent 98369dccd2 ac816e9eb5
commit e5c8fc5955
9 changed files with 100 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View File

@ -120,7 +120,9 @@ additionalProperties:
slew-rate: true slew-rate: true
gpio-hog: true gpio-hog: true
gpios: true gpios: true
input: true
input-enable: true input-enable: true
output-enable: true
output-high: true output-high: true
output-low: true output-low: true
line-name: true line-name: true

34
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
View File

@ -43,7 +43,7 @@
#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */ #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */ #define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */ #define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ #define SCU630 0x630 /* Disable GPIO Internal Pull-Down #4 */
#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
#define SCU690 0x690 /* Multi-function Pin Control #24 */ #define SCU690 0x690 /* Multi-function Pin Control #24 */
@ -2495,38 +2495,38 @@ static struct aspeed_pin_config aspeed_g6_configs[] = {
ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0), ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
/* GPIOS7 */ /* GPIOS7 */
ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23), ASPEED_PULL_DOWN_PINCONF(T24, SCU630, 23),
/* GPIOS6 */ /* GPIOS6 */
ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22), ASPEED_PULL_DOWN_PINCONF(P23, SCU630, 22),
/* GPIOS5 */ /* GPIOS5 */
ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21), ASPEED_PULL_DOWN_PINCONF(P24, SCU630, 21),
/* GPIOS4 */ /* GPIOS4 */
ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20), ASPEED_PULL_DOWN_PINCONF(R26, SCU630, 20),
/* GPIOS3*/ /* GPIOS3*/
ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19), ASPEED_PULL_DOWN_PINCONF(R24, SCU630, 19),
/* GPIOS2 */ /* GPIOS2 */
ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18), ASPEED_PULL_DOWN_PINCONF(T26, SCU630, 18),
/* GPIOS1 */ /* GPIOS1 */
ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17), ASPEED_PULL_DOWN_PINCONF(T25, SCU630, 17),
/* GPIOS0 */ /* GPIOS0 */
ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16), ASPEED_PULL_DOWN_PINCONF(R23, SCU630, 16),
/* GPIOR7 */ /* GPIOR7 */
ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15), ASPEED_PULL_DOWN_PINCONF(U26, SCU630, 15),
/* GPIOR6 */ /* GPIOR6 */
ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14), ASPEED_PULL_DOWN_PINCONF(W26, SCU630, 14),
/* GPIOR5 */ /* GPIOR5 */
ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13), ASPEED_PULL_DOWN_PINCONF(T23, SCU630, 13),
/* GPIOR4 */ /* GPIOR4 */
ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12), ASPEED_PULL_DOWN_PINCONF(U25, SCU630, 12),
/* GPIOR3*/ /* GPIOR3*/
ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11), ASPEED_PULL_DOWN_PINCONF(V26, SCU630, 11),
/* GPIOR2 */ /* GPIOR2 */
ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10), ASPEED_PULL_DOWN_PINCONF(V24, SCU630, 10),
/* GPIOR1 */ /* GPIOR1 */
ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9), ASPEED_PULL_DOWN_PINCONF(U24, SCU630, 9),
/* GPIOR0 */ /* GPIOR0 */
ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8), ASPEED_PULL_DOWN_PINCONF(V25, SCU630, 8),
/* GPIOX7 */ /* GPIOX7 */
ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31), ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),

8
drivers/pinctrl/core.c
View File

@ -2124,13 +2124,7 @@ int pinctrl_enable(struct pinctrl_dev *pctldev)
error = pinctrl_claim_hogs(pctldev); error = pinctrl_claim_hogs(pctldev);
if (error) { if (error) {
dev_err(pctldev->dev, "could not claim hogs: %i\n", dev_err(pctldev->dev, "could not claim hogs: %i\n", error);
error);
pinctrl_free_pindescs(pctldev, pctldev->desc->pins,
pctldev->desc->npins);
mutex_destroy(&pctldev->mutex);
kfree(pctldev);
return error; return error;
} }

10
drivers/pinctrl/devicetree.c
View File

@ -220,14 +220,16 @@ int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev)
for (state = 0; ; state++) { for (state = 0; ; state++) {
/* Retrieve the pinctrl-* property */ /* Retrieve the pinctrl-* property */
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state); propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
if (!propname) if (!propname) {
return -ENOMEM; ret = -ENOMEM;
goto err;
}
prop = of_find_property(np, propname, &size); prop = of_find_property(np, propname, &size);
kfree(propname); kfree(propname);
if (!prop) { if (!prop) {
if (state == 0) { if (state == 0) {
of_node_put(np); ret = -ENODEV;
return -ENODEV; goto err;
} }
break; break;
} }

78
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -231,6 +231,7 @@ static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
/* SCORE groups */ /* SCORE groups */
static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
static const unsigned int byt_score_uart3_pins[] = { 57, 61 };
static const unsigned int byt_score_pwm0_pins[] = { 94 }; static const unsigned int byt_score_pwm0_pins[] = { 94 };
static const unsigned int byt_score_pwm1_pins[] = { 95 }; static const unsigned int byt_score_pwm1_pins[] = { 95 };
@ -278,37 +279,38 @@ static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
static const struct intel_pingroup byt_score_groups[] = { static const struct intel_pingroup byt_score_groups[] = {
PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1), PIN_GROUP_GPIO("uart1_grp", byt_score_uart1_pins, 1),
PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), PIN_GROUP_GPIO("uart2_grp", byt_score_uart2_pins, 1),
PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), PIN_GROUP_GPIO("uart3_grp", byt_score_uart3_pins, 1),
PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), PIN_GROUP_GPIO("pwm0_grp", byt_score_pwm0_pins, 1),
PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1), PIN_GROUP_GPIO("pwm1_grp", byt_score_pwm1_pins, 1),
PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1), PIN_GROUP_GPIO("ssp2_grp", byt_score_ssp2_pins, 1),
PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1), PIN_GROUP_GPIO("sio_spi_grp", byt_score_sio_spi_pins, 1),
PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1), PIN_GROUP_GPIO("i2c5_grp", byt_score_i2c5_pins, 1),
PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1), PIN_GROUP_GPIO("i2c6_grp", byt_score_i2c6_pins, 1),
PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1), PIN_GROUP_GPIO("i2c4_grp", byt_score_i2c4_pins, 1),
PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1), PIN_GROUP_GPIO("i2c3_grp", byt_score_i2c3_pins, 1),
PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1), PIN_GROUP_GPIO("i2c2_grp", byt_score_i2c2_pins, 1),
PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1), PIN_GROUP_GPIO("i2c1_grp", byt_score_i2c1_pins, 1),
PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1), PIN_GROUP_GPIO("i2c0_grp", byt_score_i2c0_pins, 1),
PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1), PIN_GROUP_GPIO("ssp0_grp", byt_score_ssp0_pins, 1),
PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), PIN_GROUP_GPIO("ssp1_grp", byt_score_ssp1_pins, 1),
PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1), PIN_GROUP_GPIO("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1), PIN_GROUP_GPIO("sdio_grp", byt_score_sdio_pins, 1),
PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1), PIN_GROUP_GPIO("emmc_grp", byt_score_emmc_pins, 1),
PIN_GROUP("sata_grp", byt_score_sata_pins, 1), PIN_GROUP_GPIO("lpc_grp", byt_score_ilb_lpc_pins, 1),
PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1), PIN_GROUP_GPIO("sata_grp", byt_score_sata_pins, 1),
PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1), PIN_GROUP_GPIO("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1), PIN_GROUP_GPIO("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1), PIN_GROUP_GPIO("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1), PIN_GROUP_GPIO("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1), PIN_GROUP_GPIO("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1), PIN_GROUP_GPIO("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
PIN_GROUP_GPIO("smbus_grp", byt_score_smbus_pins, 1),
}; };
static const char * const byt_score_uart_groups[] = { static const char * const byt_score_uart_groups[] = {
"uart1_grp", "uart2_grp", "uart1_grp", "uart2_grp", "uart3_grp",
}; };
static const char * const byt_score_pwm_groups[] = { static const char * const byt_score_pwm_groups[] = {
"pwm0_grp", "pwm1_grp", "pwm0_grp", "pwm1_grp",
@ -332,12 +334,14 @@ static const char * const byt_score_plt_clk_groups[] = {
}; };
static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
static const char * const byt_score_gpio_groups[] = { static const char * const byt_score_gpio_groups[] = {
"uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", "uart1_grp_gpio", "uart2_grp_gpio", "uart3_grp_gpio", "pwm0_grp_gpio",
"ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", "pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio",
"i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", "sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio",
"sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", "i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio",
"plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", "sdcard_grp_gpio", "sdio_grp_gpio", "emmc_grp_gpio", "lpc_grp_gpio",
"plt_clk4_grp", "plt_clk5_grp", "smbus_grp", "sata_grp_gpio", "plt_clk0_grp_gpio", "plt_clk1_grp_gpio",
"plt_clk2_grp_gpio", "plt_clk3_grp_gpio", "plt_clk4_grp_gpio",
"plt_clk5_grp_gpio", "smbus_grp_gpio",
}; };
static const struct intel_function byt_score_functions[] = { static const struct intel_function byt_score_functions[] = {
@ -456,8 +460,8 @@ static const struct intel_pingroup byt_sus_groups[] = {
PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), PIN_GROUP_GPIO("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), PIN_GROUP_GPIO("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
}; };
static const char * const byt_sus_usb_groups[] = { static const char * const byt_sus_usb_groups[] = {
@ -469,7 +473,7 @@ static const char * const byt_sus_pmu_clk_groups[] = {
}; };
static const char * const byt_sus_gpio_groups[] = { static const char * const byt_sus_gpio_groups[] = {
"usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
"pmu_clk1_grp", "pmu_clk2_grp", "pmu_clk1_grp_gpio", "pmu_clk2_grp_gpio",
}; };
static const struct intel_function byt_sus_functions[] = { static const struct intel_function byt_sus_functions[] = {

4
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -179,6 +179,10 @@ struct intel_community {
.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \ .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
} }
#define PIN_GROUP_GPIO(n, p, m) \
PIN_GROUP(n, p, m), \
PIN_GROUP(n "_gpio", p, 0)
#define FUNCTION(n, g) \ #define FUNCTION(n, g) \
{ \ { \
.func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \ .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \

40
drivers/pinctrl/mediatek/pinctrl-paris.c
View File

@ -165,20 +165,21 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret); err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
break; break;
case PIN_CONFIG_INPUT_ENABLE: case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE: err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_IES, &ret);
if (!ret)
err = -EINVAL;
break;
case PIN_CONFIG_OUTPUT:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
if (err) if (err)
break; break;
/* CONFIG Current direction return value
* ------------- ----------------- ----------------------
* OUTPUT_ENABLE output 1 (= HW value)
* input 0 (= HW value)
* INPUT_ENABLE output 0 (= reverse HW value)
* input 1 (= reverse HW value)
*/
if (param == PIN_CONFIG_INPUT_ENABLE)
ret = !ret;
if (!ret) {
err = -EINVAL;
break;
}
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DO, &ret);
break; break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE: case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
@ -193,6 +194,8 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
} }
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret); err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
if (!ret)
err = -EINVAL;
break; break;
case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_DRIVE_STRENGTH:
if (!hw->soc->drive_get) if (!hw->soc->drive_get)
@ -281,26 +284,9 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
break; break;
err = hw->soc->bias_set_combo(hw, desc, 0, arg); err = hw->soc->bias_set_combo(hw, desc, 0, arg);
break; break;
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
MTK_DISABLE);
/* Keep set direction to consider the case that a GPIO pin
* does not have SMT control
*/
if (err != -ENOTSUPP)
break;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
break;
case PIN_CONFIG_INPUT_ENABLE: case PIN_CONFIG_INPUT_ENABLE:
/* regard all non-zero value as enable */ /* regard all non-zero value as enable */
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg); err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
if (err)
break;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_INPUT);
break; break;
case PIN_CONFIG_SLEW_RATE: case PIN_CONFIG_SLEW_RATE:
/* regard all non-zero value as enable */ /* regard all non-zero value as enable */

6
drivers/pinctrl/meson/pinctrl-meson-a1.c
View File

@ -250,7 +250,7 @@ static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 };
static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 };
static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 }; static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 };
static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 };
static const unsigned int pdm_dclk_pins[] = { GPIOA_9 }; static const unsigned int pdm_dclk_a_pins[] = { GPIOA_9 };
/* gen_clk */ /* gen_clk */
static const unsigned int gen_clk_x_pins[] = { GPIOX_7 }; static const unsigned int gen_clk_x_pins[] = { GPIOX_7 };
@ -591,7 +591,7 @@ static struct meson_pmx_group meson_a1_periphs_groups[] = {
GROUP(pdm_din2_a, 3), GROUP(pdm_din2_a, 3),
GROUP(pdm_din1_a, 3), GROUP(pdm_din1_a, 3),
GROUP(pdm_din0_a, 3), GROUP(pdm_din0_a, 3),
GROUP(pdm_dclk, 3), GROUP(pdm_dclk_a, 3),
GROUP(pwm_c_a, 3), GROUP(pwm_c_a, 3),
GROUP(pwm_b_a, 3), GROUP(pwm_b_a, 3),
@ -755,7 +755,7 @@ static const char * const spi_a_groups[] = {
static const char * const pdm_groups[] = { static const char * const pdm_groups[] = {
"pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a", "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
"pdm_din1_a", "pdm_din0_a", "pdm_dclk", "pdm_din1_a", "pdm_din0_a", "pdm_dclk_a",
}; };
static const char * const gen_clk_groups[] = { static const char * const gen_clk_groups[] = {

14
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -2045,7 +2045,9 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
struct irq_data *data; struct irq_data *data;
unsigned long flags;
unsigned int virq; unsigned int virq;
int ret;
if (!pctrl->hwirq[i]) if (!pctrl->hwirq[i])
continue; continue;
@ -2063,8 +2065,18 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
continue; continue;
} }
if (!irqd_irq_disabled(data)) /*
* This has to be atomically executed to protect against a concurrent
* interrupt.
*/
raw_spin_lock_irqsave(&pctrl->lock.rlock, flags);
ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data));
if (!ret && !irqd_irq_disabled(data))
rzg2l_gpio_irq_enable(data); rzg2l_gpio_irq_enable(data);
raw_spin_unlock_irqrestore(&pctrl->lock.rlock, flags);
if (ret)
dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);
} }
} }