scsi: ufs: ufs-unisoc: Add support for Unisoc UFS host controller
Add driver code for Unisoc UFS host controller, along with UFS initialization. Signed-off-by: Zhe Wang <zhe.wang1@unisoc.com> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Zhe Wang
Martin K. Petersen
parent
aa67971b27
commit
df7320bac3
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@ -128,3 +128,15 @@ config SCSI_UFS_EXYNOS
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config SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
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bool
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default y if SCSI_UFS_EXYNOS && SCSI_UFS_CRYPTO
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config SCSI_UFS_SPRD
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tristate "Unisoc specific hooks to UFS controller platform driver"
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depends on SCSI_UFSHCD_PLATFORM && (ARCH_SPRD || COMPILE_TEST)
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help
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This selects the Unisoc specific additions to UFSHCD platform driver.
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UFS host on Unisoc needs some vendor specific configuration before
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accessing the hardware which includes PHY configuration and vendor
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specific registers.
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Select this if you have UFS controller on Unisoc chipset.
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If unsure, say N.
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@ -12,4 +12,5 @@ obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
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obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
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obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
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obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
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obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o
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obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
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@ -0,0 +1,458 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UNISOC UFS Host Controller driver
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*
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* Copyright (C) 2022 Unisoc, Inc.
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* Author: Zhe Wang <zhe.wang1@unisoc.com>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <ufs/ufshcd.h>
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#include "ufshcd-pltfrm.h"
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#include "ufs-sprd.h"
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static const struct of_device_id ufs_sprd_of_match[];
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static struct ufs_sprd_priv *ufs_sprd_get_priv_data(struct ufs_hba *hba)
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{
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struct ufs_sprd_host *host = ufshcd_get_variant(hba);
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WARN_ON(!host->priv);
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return host->priv;
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}
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static void ufs_sprd_regmap_update(struct ufs_sprd_priv *priv, unsigned int index,
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unsigned int reg, unsigned int bits, unsigned int val)
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{
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regmap_update_bits(priv->sysci[index].regmap, reg, bits, val);
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}
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static void ufs_sprd_regmap_read(struct ufs_sprd_priv *priv, unsigned int index,
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unsigned int reg, unsigned int *val)
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{
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regmap_read(priv->sysci[index].regmap, reg, val);
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}
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static void ufs_sprd_get_unipro_ver(struct ufs_hba *hba)
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{
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struct ufs_sprd_host *host = ufshcd_get_variant(hba);
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if (ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &host->unipro_ver))
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host->unipro_ver = 0;
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}
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static void ufs_sprd_ctrl_uic_compl(struct ufs_hba *hba, bool enable)
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{
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u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
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if (enable == true)
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set |= UIC_COMMAND_COMPL;
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else
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set &= ~UIC_COMMAND_COMPL;
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ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
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}
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static int ufs_sprd_get_reset_ctrl(struct device *dev, struct ufs_sprd_rst *rci)
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{
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rci->rc = devm_reset_control_get(dev, rci->name);
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if (IS_ERR(rci->rc)) {
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dev_err(dev, "failed to get reset ctrl:%s\n", rci->name);
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return PTR_ERR(rci->rc);
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}
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return 0;
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}
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static int ufs_sprd_get_syscon_reg(struct device *dev, struct ufs_sprd_syscon *sysci)
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{
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sysci->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, sysci->name);
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if (IS_ERR(sysci->regmap)) {
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dev_err(dev, "failed to get ufs syscon:%s\n", sysci->name);
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return PTR_ERR(sysci->regmap);
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}
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return 0;
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}
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static int ufs_sprd_get_vreg(struct device *dev, struct ufs_sprd_vreg *vregi)
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{
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vregi->vreg = devm_regulator_get(dev, vregi->name);
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if (IS_ERR(vregi->vreg)) {
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dev_err(dev, "failed to get vreg:%s\n", vregi->name);
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return PTR_ERR(vregi->vreg);
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}
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return 0;
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}
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static int ufs_sprd_parse_dt(struct device *dev, struct ufs_hba *hba, struct ufs_sprd_host *host)
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{
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u32 i;
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struct ufs_sprd_priv *priv = host->priv;
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int ret = 0;
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/* Parse UFS reset ctrl info */
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for (i = 0; i < SPRD_UFS_RST_MAX; i++) {
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if (!priv->rci[i].name)
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continue;
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ret = ufs_sprd_get_reset_ctrl(dev, &priv->rci[i]);
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if (ret)
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goto out;
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}
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/* Parse UFS syscon reg info */
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for (i = 0; i < SPRD_UFS_SYSCON_MAX; i++) {
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if (!priv->sysci[i].name)
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continue;
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ret = ufs_sprd_get_syscon_reg(dev, &priv->sysci[i]);
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if (ret)
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goto out;
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}
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/* Parse UFS vreg info */
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for (i = 0; i < SPRD_UFS_VREG_MAX; i++) {
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if (!priv->vregi[i].name)
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continue;
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ret = ufs_sprd_get_vreg(dev, &priv->vregi[i]);
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if (ret)
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goto out;
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}
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out:
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return ret;
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}
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static int ufs_sprd_common_init(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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struct ufs_sprd_host *host;
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struct platform_device __maybe_unused *pdev = to_platform_device(dev);
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const struct of_device_id *of_id;
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int ret = 0;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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of_id = of_match_node(ufs_sprd_of_match, pdev->dev.of_node);
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if (of_id->data != NULL)
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host->priv = container_of(of_id->data, struct ufs_sprd_priv,
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ufs_hba_sprd_vops);
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host->hba = hba;
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ufshcd_set_variant(hba, host);
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hba->caps |= UFSHCD_CAP_CLK_GATING |
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UFSHCD_CAP_CRYPTO |
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UFSHCD_CAP_WB_EN;
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hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS;
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ret = ufs_sprd_parse_dt(dev, hba, host);
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return ret;
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}
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static int sprd_ufs_pwr_change_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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struct ufs_sprd_host *host = ufshcd_get_variant(hba);
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if (status == PRE_CHANGE) {
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memcpy(dev_req_params, dev_max_params,
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sizeof(struct ufs_pa_layer_attr));
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if (host->unipro_ver >= UFS_UNIPRO_VER_1_8)
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ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx,
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PA_INITIAL_ADAPT);
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}
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return 0;
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}
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static int ufs_sprd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
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enum ufs_notify_change_status status)
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{
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unsigned long flags;
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if (status == PRE_CHANGE) {
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if (ufshcd_is_auto_hibern8_supported(hba)) {
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spin_lock_irqsave(hba->host->host_lock, flags);
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ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
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spin_unlock_irqrestore(hba->host->host_lock, flags);
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}
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}
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return 0;
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}
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static void ufs_sprd_n6_host_reset(struct ufs_hba *hba)
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{
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struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
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dev_info(hba->dev, "ufs host reset!\n");
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reset_control_assert(priv->rci[SPRD_UFSHCI_SOFT_RST].rc);
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usleep_range(1000, 1100);
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reset_control_deassert(priv->rci[SPRD_UFSHCI_SOFT_RST].rc);
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}
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static int ufs_sprd_n6_device_reset(struct ufs_hba *hba)
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{
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struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
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dev_info(hba->dev, "ufs device reset!\n");
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reset_control_assert(priv->rci[SPRD_UFS_DEV_RST].rc);
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usleep_range(1000, 1100);
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reset_control_deassert(priv->rci[SPRD_UFS_DEV_RST].rc);
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return 0;
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}
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static void ufs_sprd_n6_key_acc_enable(struct ufs_hba *hba)
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{
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u32 val;
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u32 retry = 10;
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struct arm_smccc_res res;
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check_hce:
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/* Key access only can be enabled under HCE enable */
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val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
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if (!(val & CONTROLLER_ENABLE)) {
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ufs_sprd_n6_host_reset(hba);
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val |= CONTROLLER_ENABLE;
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ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
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usleep_range(1000, 1100);
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if (retry) {
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retry--;
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goto check_hce;
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}
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goto disable_crypto;
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}
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arm_smccc_smc(SPRD_SIP_SVC_STORAGE_UFS_CRYPTO_ENABLE,
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0, 0, 0, 0, 0, 0, 0, &res);
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if (!res.a0)
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return;
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disable_crypto:
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dev_err(hba->dev, "key reg access enable fail, disable crypto\n");
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hba->caps &= ~UFSHCD_CAP_CRYPTO;
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}
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static int ufs_sprd_n6_init(struct ufs_hba *hba)
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{
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struct ufs_sprd_priv *priv;
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int ret = 0;
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ret = ufs_sprd_common_init(hba);
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if (ret != 0)
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return ret;
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priv = ufs_sprd_get_priv_data(hba);
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ret = regulator_enable(priv->vregi[SPRD_UFS_VDD_MPHY].vreg);
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if (ret)
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return -ENODEV;
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if (hba->caps & UFSHCD_CAP_CRYPTO)
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ufs_sprd_n6_key_acc_enable(hba);
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return 0;
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}
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static int ufs_sprd_n6_phy_init(struct ufs_hba *hba)
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{
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int ret = 0;
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uint32_t val = 0;
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uint32_t retry = 10;
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uint32_t offset;
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struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBREFCLKCTRL2), 0x90);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBCRCTRL), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL,
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UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), 0x01);
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do {
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/* phy_sram_init_done */
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ufs_sprd_regmap_read(priv, SPRD_UFS_ANLG, 0xc, &val);
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if ((val & 0x1) == 0x1) {
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for (offset = 0x40; offset < 0x42; offset++) {
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/* Lane afe calibration */
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRLSB), 0x1c);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRMSB), offset);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRLSB), 0x04);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRMSB), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGRDWRSEL), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
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}
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goto update_phy;
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}
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udelay(1000);
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retry--;
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} while (retry > 0);
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ret = -ETIMEDOUT;
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goto out;
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update_phy:
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/* phy_sram_ext_ld_done */
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ufs_sprd_regmap_update(priv, SPRD_UFS_ANLG, 0xc, 0x2, 0);
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ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
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ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0x0);
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out:
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return ret;
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}
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static int sprd_ufs_n6_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
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if (status == PRE_CHANGE) {
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/* phy_sram_ext_ld_done */
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ufs_sprd_regmap_update(priv, SPRD_UFS_ANLG, 0xc, 0x2, 0x2);
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/* phy_sram_bypass */
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ufs_sprd_regmap_update(priv, SPRD_UFS_ANLG, 0xc, 0x4, 0x4);
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ufs_sprd_n6_host_reset(hba);
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if (hba->caps & UFSHCD_CAP_CRYPTO)
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ufs_sprd_n6_key_acc_enable(hba);
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}
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if (status == POST_CHANGE) {
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err = ufs_sprd_n6_phy_init(hba);
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if (err) {
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dev_err(hba->dev, "Phy setup failed (%d)\n", err);
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goto out;
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}
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ufs_sprd_get_unipro_ver(hba);
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}
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out:
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return err;
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}
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static void sprd_ufs_n6_h8_notify(struct ufs_hba *hba,
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enum uic_cmd_dme cmd,
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enum ufs_notify_change_status status)
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{
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struct ufs_sprd_priv *priv = ufs_sprd_get_priv_data(hba);
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if (status == PRE_CHANGE) {
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if (cmd == UIC_CMD_DME_HIBER_ENTER)
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/*
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* Disable UIC COMPL INTR to prevent access to UFSHCI after
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* checking HCS.UPMCRS
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*/
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ufs_sprd_ctrl_uic_compl(hba, false);
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if (cmd == UIC_CMD_DME_HIBER_EXIT) {
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ufs_sprd_regmap_update(priv, SPRD_UFS_AON_APB, APB_UFSDEV_REG,
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APB_UFSDEV_REFCLK_EN, APB_UFSDEV_REFCLK_EN);
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ufs_sprd_regmap_update(priv, SPRD_UFS_AON_APB, APB_USB31PLL_CTRL,
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APB_USB31PLLV_REF2MPHY, APB_USB31PLLV_REF2MPHY);
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}
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}
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if (status == POST_CHANGE) {
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if (cmd == UIC_CMD_DME_HIBER_EXIT)
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ufs_sprd_ctrl_uic_compl(hba, true);
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if (cmd == UIC_CMD_DME_HIBER_ENTER) {
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ufs_sprd_regmap_update(priv, SPRD_UFS_AON_APB, APB_UFSDEV_REG,
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APB_UFSDEV_REFCLK_EN, 0);
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ufs_sprd_regmap_update(priv, SPRD_UFS_AON_APB, APB_USB31PLL_CTRL,
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APB_USB31PLLV_REF2MPHY, 0);
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}
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}
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}
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static struct ufs_sprd_priv n6_ufs = {
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.rci[SPRD_UFSHCI_SOFT_RST] = { .name = "controller", },
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.rci[SPRD_UFS_DEV_RST] = { .name = "device", },
|
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|
||||
.sysci[SPRD_UFS_ANLG] = { .name = "sprd,ufs-anlg-syscon", },
|
||||
.sysci[SPRD_UFS_AON_APB] = { .name = "sprd,aon-apb-syscon", },
|
||||
|
||||
.vregi[SPRD_UFS_VDD_MPHY] = { .name = "vdd-mphy", },
|
||||
|
||||
.ufs_hba_sprd_vops = {
|
||||
.name = "sprd,ums9620-ufs",
|
||||
.init = ufs_sprd_n6_init,
|
||||
.hce_enable_notify = sprd_ufs_n6_hce_enable_notify,
|
||||
.pwr_change_notify = sprd_ufs_pwr_change_notify,
|
||||
.hibern8_notify = sprd_ufs_n6_h8_notify,
|
||||
.device_reset = ufs_sprd_n6_device_reset,
|
||||
.suspend = ufs_sprd_suspend,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id __maybe_unused ufs_sprd_of_match[] = {
|
||||
{ .compatible = "sprd,ums9620-ufs", .data = &n6_ufs.ufs_hba_sprd_vops},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ufs_sprd_of_match);
|
||||
|
||||
static int ufs_sprd_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err;
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct of_device_id *of_id;
|
||||
|
||||
of_id = of_match_node(ufs_sprd_of_match, dev->of_node);
|
||||
err = ufshcd_pltfrm_init(pdev, of_id->data);
|
||||
if (err)
|
||||
dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ufs_sprd_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
||||
|
||||
pm_runtime_get_sync(&(pdev)->dev);
|
||||
ufshcd_remove(hba);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops ufs_sprd_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
|
||||
SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
|
||||
.prepare = ufshcd_suspend_prepare,
|
||||
.complete = ufshcd_resume_complete,
|
||||
};
|
||||
|
||||
static struct platform_driver ufs_sprd_pltform = {
|
||||
.probe = ufs_sprd_probe,
|
||||
.remove = ufs_sprd_remove,
|
||||
.shutdown = ufshcd_pltfrm_shutdown,
|
||||
.driver = {
|
||||
.name = "ufshcd-sprd",
|
||||
.pm = &ufs_sprd_pm_ops,
|
||||
.of_match_table = of_match_ptr(ufs_sprd_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(ufs_sprd_pltform);
|
||||
|
||||
MODULE_AUTHOR("Zhe Wang <zhe.wang1@unisoc.com>");
|
||||
MODULE_DESCRIPTION("Unisoc UFS Host Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* UNISOC UFS Host Controller driver
|
||||
*
|
||||
* Copyright (C) 2022 Unisoc, Inc.
|
||||
* Author: Zhe Wang <zhe.wang1@unisoc.com>
|
||||
*/
|
||||
|
||||
#ifndef _UFS_SPRD_H_
|
||||
#define _UFS_SPRD_H_
|
||||
|
||||
/* Vendor specific attributes */
|
||||
#define RXSQCONTROL 0x8009
|
||||
#define CBRATESEL 0x8114
|
||||
#define CBCREGADDRLSB 0x8116
|
||||
#define CBCREGADDRMSB 0x8117
|
||||
#define CBCREGWRLSB 0x8118
|
||||
#define CBCREGWRMSB 0x8119
|
||||
#define CBCREGRDWRSEL 0x811C
|
||||
#define CBCRCTRL 0x811F
|
||||
#define CBREFCLKCTRL2 0x8132
|
||||
#define VS_MPHYDISABLE 0xD0C1
|
||||
|
||||
#define APB_UFSDEV_REG 0xCE8
|
||||
#define APB_UFSDEV_REFCLK_EN 0x2
|
||||
#define APB_USB31PLL_CTRL 0xCFC
|
||||
#define APB_USB31PLLV_REF2MPHY 0x1
|
||||
|
||||
#define SPRD_SIP_SVC_STORAGE_UFS_CRYPTO_ENABLE \
|
||||
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
|
||||
ARM_SMCCC_SMC_32, \
|
||||
ARM_SMCCC_OWNER_SIP, \
|
||||
0x0301)
|
||||
|
||||
enum SPRD_UFS_RST_INDEX {
|
||||
SPRD_UFSHCI_SOFT_RST,
|
||||
SPRD_UFS_DEV_RST,
|
||||
|
||||
SPRD_UFS_RST_MAX
|
||||
};
|
||||
|
||||
enum SPRD_UFS_SYSCON_INDEX {
|
||||
SPRD_UFS_ANLG,
|
||||
SPRD_UFS_AON_APB,
|
||||
|
||||
SPRD_UFS_SYSCON_MAX
|
||||
};
|
||||
|
||||
enum SPRD_UFS_VREG_INDEX {
|
||||
SPRD_UFS_VDD_MPHY,
|
||||
|
||||
SPRD_UFS_VREG_MAX
|
||||
};
|
||||
|
||||
struct ufs_sprd_rst {
|
||||
const char *name;
|
||||
struct reset_control *rc;
|
||||
};
|
||||
|
||||
struct ufs_sprd_syscon {
|
||||
const char *name;
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
struct ufs_sprd_vreg {
|
||||
const char *name;
|
||||
struct regulator *vreg;
|
||||
};
|
||||
|
||||
struct ufs_sprd_priv {
|
||||
struct ufs_sprd_rst rci[SPRD_UFS_RST_MAX];
|
||||
struct ufs_sprd_syscon sysci[SPRD_UFS_SYSCON_MAX];
|
||||
struct ufs_sprd_vreg vregi[SPRD_UFS_VREG_MAX];
|
||||
const struct ufs_hba_variant_ops ufs_hba_sprd_vops;
|
||||
};
|
||||
|
||||
struct ufs_sprd_host {
|
||||
struct ufs_hba *hba;
|
||||
struct ufs_sprd_priv *priv;
|
||||
void __iomem *ufs_dbg_mmio;
|
||||
|
||||
enum ufs_unipro_ver unipro_ver;
|
||||
};
|
||||
|
||||
#endif /* _UFS_SPRD_H_ */
|
||||
Loading…
Reference in New Issue