gpio: tangier: Introduce Intel Tangier GPIO driver
Intel Elkhart Lake and Merrifield platforms have same GPIO IP. Intel Tangier implements the common GPIO functionalities for both Elkhart Lake and Merrifield platforms. Signed-off-by: Pandith N <pandith.n@intel.com> Co-developed-by: Raag Jadav <raag.jadav@intel.com> Signed-off-by: Raag Jadav <raag.jadav@intel.com> Co-developed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Pandith N
Andy Shevchenko
parent
380c7ba392
commit
d2c19e89e0
@ -10287,6 +10287,7 @@ F: drivers/gpio/gpio-ml-ioh.c
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F: drivers/gpio/gpio-pch.c
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F: drivers/gpio/gpio-sch.c
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F: drivers/gpio/gpio-sodaville.c
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F: drivers/gpio/gpio-tangier.c
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INTEL GVT-g DRIVERS (Intel GPU Virtualization)
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M: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -619,6 +619,14 @@ config GPIO_SYSCON
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help
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Say yes here to support GPIO functionality though SYSCON driver.
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config GPIO_TANGIER
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tristate
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select GPIOLIB_IRQCHIP
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help
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GPIO support for Intel Tangier and compatible platforms.
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If built as a module its name will be gpio-tangier.
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config GPIO_TB10X
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bool
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select GPIO_GENERIC
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@ -145,6 +145,7 @@ obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o
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obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
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obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o
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obj-$(CONFIG_GPIO_SYSCON) += gpio-syscon.o
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obj-$(CONFIG_GPIO_TANGIER) += gpio-tangier.o
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obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o
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obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
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obj-$(CONFIG_GPIO_TEGRA186) += gpio-tegra186.o
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536
drivers/gpio/gpio-tangier.c
Normal file
536
drivers/gpio/gpio-tangier.c
Normal file
@ -0,0 +1,536 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Tangier GPIO driver
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*
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* Copyright (c) 2016, 2021, 2023 Intel Corporation.
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*
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* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Pandith N <pandith.n@intel.com>
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* Raag Jadav <raag.jadav@intel.com>
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/spinlock.h>
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#include <linux/string_helpers.h>
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#include <linux/types.h>
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#include <linux/gpio/driver.h>
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#include "gpio-tangier.h"
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#define GCCR 0x000 /* Controller configuration */
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#define GPLR 0x004 /* Pin level r/o */
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#define GPDR 0x01c /* Pin direction */
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#define GPSR 0x034 /* Pin set w/o */
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#define GPCR 0x04c /* Pin clear w/o */
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#define GRER 0x064 /* Rising edge detect */
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#define GFER 0x07c /* Falling edge detect */
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#define GFBR 0x094 /* Glitch filter bypass */
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#define GIMR 0x0ac /* Interrupt mask */
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#define GISR 0x0c4 /* Interrupt source */
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#define GITR 0x300 /* Input type */
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#define GLPR 0x318 /* Level input polarity */
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/**
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* struct tng_gpio_context - Context to be saved during suspend-resume
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* @level: Pin level
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* @gpdr: Pin direction
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* @grer: Rising edge detect enable
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* @gfer: Falling edge detect enable
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* @gimr: Interrupt mask
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* @gwmr: Wake mask
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*/
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struct tng_gpio_context {
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u32 level;
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u32 gpdr;
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u32 grer;
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u32 gfer;
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u32 gimr;
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u32 gwmr;
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};
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
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unsigned int reg)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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u8 reg_offset = offset / 32;
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return priv->reg_base + reg + reg_offset * 4;
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}
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static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset,
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unsigned int reg, u8 *bit)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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u8 reg_offset = offset / 32;
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u8 shift = offset % 32;
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*bit = shift;
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return priv->reg_base + reg + reg_offset * 4;
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}
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static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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void __iomem *gplr;
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u8 shift;
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gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift);
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return !!(readl(gplr) & BIT(shift));
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}
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static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *reg;
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u8 shift;
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reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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writel(BIT(shift), reg);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *gpdr;
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u32 value;
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u8 shift;
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gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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value = readl(gpdr);
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value &= ~BIT(shift);
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writel(value, gpdr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *gpdr;
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u8 shift;
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gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
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tng_gpio_set(chip, offset, value);
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raw_spin_lock_irqsave(&priv->lock, flags);
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value = readl(gpdr);
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value |= BIT(shift);
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writel(value, gpdr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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void __iomem *gpdr;
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u8 shift;
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gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
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if (readl(gpdr) & BIT(shift))
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
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unsigned int debounce)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *gfbr;
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u32 value;
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u8 shift;
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gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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value = readl(gfbr);
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if (debounce)
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value &= ~BIT(shift);
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else
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value |= BIT(shift);
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writel(value, gfbr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
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unsigned long config)
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{
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u32 debounce;
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switch (pinconf_to_config_param(config)) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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return gpiochip_generic_config(chip, offset, config);
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case PIN_CONFIG_INPUT_DEBOUNCE:
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debounce = pinconf_to_config_argument(config);
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return tng_gpio_set_debounce(chip, offset, debounce);
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default:
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return -ENOTSUPP;
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}
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}
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static void tng_irq_ack(struct irq_data *d)
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{
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struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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unsigned long flags;
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void __iomem *gisr;
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u8 shift;
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gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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writel(BIT(shift), gisr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)
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{
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unsigned long flags;
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void __iomem *gimr;
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u32 value;
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u8 shift;
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gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift);
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raw_spin_lock_irqsave(&priv->lock, flags);
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value = readl(gimr);
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if (unmask)
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value |= BIT(shift);
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else
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value &= ~BIT(shift);
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writel(value, gimr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void tng_irq_mask(struct irq_data *d)
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{
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struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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tng_irq_unmask_mask(priv, gpio, false);
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gpiochip_disable_irq(&priv->chip, gpio);
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}
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static void tng_irq_unmask(struct irq_data *d)
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{
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struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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gpiochip_enable_irq(&priv->chip, gpio);
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tng_irq_unmask_mask(priv, gpio, true);
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}
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static int tng_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tng_gpio *priv = gpiochip_get_data(gc);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
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void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
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void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
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void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
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u8 shift = gpio % 32;
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&priv->lock, flags);
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value = readl(grer);
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if (type & IRQ_TYPE_EDGE_RISING)
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value |= BIT(shift);
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else
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value &= ~BIT(shift);
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writel(value, grer);
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value = readl(gfer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value |= BIT(shift);
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else
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value &= ~BIT(shift);
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writel(value, gfer);
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/*
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* To prevent glitches from triggering an unintended level interrupt,
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* configure GLPR register first and then configure GITR.
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*/
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value = readl(glpr);
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if (type & IRQ_TYPE_LEVEL_LOW)
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value |= BIT(shift);
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else
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value &= ~BIT(shift);
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writel(value, glpr);
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if (type & IRQ_TYPE_LEVEL_MASK) {
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value = readl(gitr);
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value |= BIT(shift);
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writel(value, gitr);
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irq_set_handler_locked(d, handle_level_irq);
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} else if (type & IRQ_TYPE_EDGE_BOTH) {
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value = readl(gitr);
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value &= ~BIT(shift);
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writel(value, gitr);
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irq_set_handler_locked(d, handle_edge_irq);
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}
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int tng_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tng_gpio *priv = gpiochip_get_data(gc);
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irq_hw_number_t gpio = irqd_to_hwirq(d);
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void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr);
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void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr);
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u8 shift = gpio % 32;
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&priv->lock, flags);
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/* Clear the existing wake status */
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writel(BIT(shift), gwsr);
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value = readl(gwmr);
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if (on)
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value |= BIT(shift);
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else
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value &= ~BIT(shift);
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writel(value, gwmr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);
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return 0;
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}
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static const struct irq_chip tng_irqchip = {
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.name = "gpio-tangier",
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.irq_ack = tng_irq_ack,
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.irq_mask = tng_irq_mask,
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.irq_unmask = tng_irq_unmask,
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.irq_set_type = tng_irq_set_type,
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.irq_set_wake = tng_irq_set_wake,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static void tng_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct tng_gpio *priv = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned long base, gpio;
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chained_irq_enter(irqchip, desc);
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/* Check GPIO controller to check which pin triggered the interrupt */
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for (base = 0; base < priv->chip.ngpio; base += 32) {
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void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
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void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
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unsigned long pending, enabled;
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pending = readl(gisr);
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enabled = readl(gimr);
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/* Only interrupts that are enabled */
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pending &= enabled;
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for_each_set_bit(gpio, &pending, 32)
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generic_handle_domain_irq(gc->irq.domain, base + gpio);
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}
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chained_irq_exit(irqchip, desc);
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}
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static int tng_irq_init_hw(struct gpio_chip *chip)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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void __iomem *reg;
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unsigned int base;
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for (base = 0; base < priv->chip.ngpio; base += 32) {
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/* Clear the rising-edge detect register */
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reg = gpio_reg(&priv->chip, base, GRER);
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writel(0, reg);
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/* Clear the falling-edge detect register */
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reg = gpio_reg(&priv->chip, base, GFER);
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writel(0, reg);
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}
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return 0;
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}
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static int tng_gpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct tng_gpio *priv = gpiochip_get_data(chip);
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const struct tng_gpio_pinrange *range;
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unsigned int i;
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int ret;
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for (i = 0; i < priv->pin_info.nranges; i++) {
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range = &priv->pin_info.pin_ranges[i];
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ret = gpiochip_add_pin_range(&priv->chip,
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priv->pin_info.name,
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range->gpio_base,
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range->pin_base,
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range->npins);
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if (ret) {
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dev_err(priv->dev, "failed to add GPIO pin range\n");
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return ret;
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}
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}
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return 0;
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}
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int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio)
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{
|
||||
const struct tng_gpio_info *info = &gpio->info;
|
||||
struct gpio_irq_chip *girq;
|
||||
int ret;
|
||||
|
||||
gpio->ctx = devm_kcalloc(dev, DIV_ROUND_UP(info->ngpio, 32), sizeof(*gpio->ctx), GFP_KERNEL);
|
||||
if (!gpio->ctx)
|
||||
return -ENOMEM;
|
||||
|
||||
gpio->chip.label = dev_name(dev);
|
||||
gpio->chip.parent = dev;
|
||||
gpio->chip.request = gpiochip_generic_request;
|
||||
gpio->chip.free = gpiochip_generic_free;
|
||||
gpio->chip.direction_input = tng_gpio_direction_input;
|
||||
gpio->chip.direction_output = tng_gpio_direction_output;
|
||||
gpio->chip.get = tng_gpio_get;
|
||||
gpio->chip.set = tng_gpio_set;
|
||||
gpio->chip.get_direction = tng_gpio_get_direction;
|
||||
gpio->chip.set_config = tng_gpio_set_config;
|
||||
gpio->chip.base = info->base;
|
||||
gpio->chip.ngpio = info->ngpio;
|
||||
gpio->chip.can_sleep = false;
|
||||
gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges;
|
||||
|
||||
raw_spin_lock_init(&gpio->lock);
|
||||
|
||||
girq = &gpio->chip.irq;
|
||||
gpio_irq_chip_set_chip(girq, &tng_irqchip);
|
||||
girq->init_hw = tng_irq_init_hw;
|
||||
girq->parent_handler = tng_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(dev, girq->num_parents,
|
||||
sizeof(*girq->parents), GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
|
||||
girq->parents[0] = gpio->irq;
|
||||
girq->first = info->first;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_bad_irq;
|
||||
|
||||
ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "gpiochip_add error\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER);
|
||||
|
||||
int tng_gpio_suspend(struct device *dev)
|
||||
{
|
||||
struct tng_gpio *priv = dev_get_drvdata(dev);
|
||||
struct tng_gpio_context *ctx = priv->ctx;
|
||||
unsigned long flags;
|
||||
unsigned int base;
|
||||
|
||||
raw_spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
|
||||
/* GPLR is RO, values read will be restored using GPSR */
|
||||
ctx->level = readl(gpio_reg(&priv->chip, base, GPLR));
|
||||
|
||||
ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR));
|
||||
ctx->grer = readl(gpio_reg(&priv->chip, base, GRER));
|
||||
ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER));
|
||||
ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR));
|
||||
|
||||
ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER);
|
||||
|
||||
int tng_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct tng_gpio *priv = dev_get_drvdata(dev);
|
||||
struct tng_gpio_context *ctx = priv->ctx;
|
||||
unsigned long flags;
|
||||
unsigned int base;
|
||||
|
||||
raw_spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
|
||||
/* GPLR is RO, values read will be restored using GPSR */
|
||||
writel(ctx->level, gpio_reg(&priv->chip, base, GPSR));
|
||||
|
||||
writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR));
|
||||
writel(ctx->grer, gpio_reg(&priv->chip, base, GRER));
|
||||
writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER));
|
||||
writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR));
|
||||
|
||||
writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER);
|
||||
|
||||
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
||||
MODULE_AUTHOR("Pandith N <pandith.n@intel.com>");
|
||||
MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>");
|
||||
MODULE_DESCRIPTION("Intel Tangier GPIO driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
107
drivers/gpio/gpio-tangier.h
Normal file
107
drivers/gpio/gpio-tangier.h
Normal file
@ -0,0 +1,107 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Intel Tangier GPIO functions
|
||||
*
|
||||
* Copyright (c) 2016, 2021, 2023 Intel Corporation.
|
||||
*
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Pandith N <pandith.n@intel.com>
|
||||
* Raag Jadav <raag.jadav@intel.com>
|
||||
*/
|
||||
|
||||
#ifndef _GPIO_TANGIER_H_
|
||||
#define _GPIO_TANGIER_H_
|
||||
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device;
|
||||
|
||||
struct tng_gpio_context;
|
||||
|
||||
/**
|
||||
* struct tng_wake_regs - Platform specific wake registers
|
||||
* @gwmr: Wake mask
|
||||
* @gwsr: Wake source
|
||||
* @gsir: Secure input
|
||||
*/
|
||||
struct tng_wake_regs {
|
||||
u32 gwmr;
|
||||
u32 gwsr;
|
||||
u32 gsir;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tng_gpio_pinrange - Map pin numbers to gpio numbers
|
||||
* @gpio_base: Starting GPIO number of this range
|
||||
* @pin_base: Starting pin number of this range
|
||||
* @npins: Number of pins in this range
|
||||
*/
|
||||
struct tng_gpio_pinrange {
|
||||
unsigned int gpio_base;
|
||||
unsigned int pin_base;
|
||||
unsigned int npins;
|
||||
};
|
||||
|
||||
#define GPIO_PINRANGE(gstart, gend, pstart) \
|
||||
(struct tng_gpio_pinrange) { \
|
||||
.gpio_base = (gstart), \
|
||||
.pin_base = (pstart), \
|
||||
.npins = (gend) - (gstart) + 1, \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct tng_gpio_pin_info - Platform specific pinout information
|
||||
* @pin_ranges: Pin to GPIO mapping
|
||||
* @nranges: Number of pin ranges
|
||||
* @name: Respective pinctrl device name
|
||||
*/
|
||||
struct tng_gpio_pin_info {
|
||||
const struct tng_gpio_pinrange *pin_ranges;
|
||||
unsigned int nranges;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tng_gpio_info - Platform specific GPIO and IRQ information
|
||||
* @base: GPIO base to start numbering with
|
||||
* @ngpio: Amount of GPIOs supported by the controller
|
||||
* @first: First IRQ to start numbering with
|
||||
*/
|
||||
struct tng_gpio_info {
|
||||
int base;
|
||||
u16 ngpio;
|
||||
unsigned int first;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tng_gpio - Platform specific private data
|
||||
* @chip: Instance of the struct gpio_chip
|
||||
* @reg_base: Base address of MMIO registers
|
||||
* @irq: Interrupt for the GPIO device
|
||||
* @lock: Synchronization lock to prevent I/O race conditions
|
||||
* @dev: The GPIO device
|
||||
* @ctx: Context to be saved during suspend-resume
|
||||
* @wake_regs: Platform specific wake registers
|
||||
* @pin_info: Platform specific pinout information
|
||||
* @info: Platform specific GPIO and IRQ information
|
||||
*/
|
||||
struct tng_gpio {
|
||||
struct gpio_chip chip;
|
||||
void __iomem *reg_base;
|
||||
int irq;
|
||||
raw_spinlock_t lock;
|
||||
struct device *dev;
|
||||
struct tng_gpio_context *ctx;
|
||||
struct tng_wake_regs wake_regs;
|
||||
struct tng_gpio_pin_info pin_info;
|
||||
struct tng_gpio_info info;
|
||||
};
|
||||
|
||||
int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio);
|
||||
|
||||
int tng_gpio_suspend(struct device *dev);
|
||||
int tng_gpio_resume(struct device *dev);
|
||||
|
||||
#endif /* _GPIO_TANGIER_H_ */
|
||||
Loading…
Reference in New Issue
Block a user