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LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE 

LoongArch has hardware page coloring for L1 Cache, so we don't have
cache aliases. But SFB (Store Fill Buffer) still has aliases. So we
define SHMLBA to SZ_64K previously. But there are losts of applications
use PAGE_SIZE rather than SHMLBA to mmap() file pages and shared pages.
Of course we can fix them one by one, but not easy.

On the other hand, we can simply disable SFB for 4KB page size to fix
cache alias (there will be performance decrease, but acceptable), and
in future we will fix SFB in hardware. So we can safely define SHMLBA to
PAGE_SIZE (use the generic shmparam.h) to make life easier.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen 2024-01-17 12:43:08 +08:00
parent 9499daeade
commit d23b77953f
2 changed files with 10 additions and 12 deletions
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12
arch/loongarch/include/asm/shmparam.h
View File

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
*/
#ifndef _ASM_SHMPARAM_H
#define _ASM_SHMPARAM_H
#define __ARCH_FORCE_SHMLBA 1
#define SHMLBA SZ_64K /* attach addr a multiple of this */
#endif /* _ASM_SHMPARAM_H */

10
arch/loongarch/kernel/head.S
View File

@ -75,6 +75,11 @@ SYM_CODE_START(kernel_entry) # kernel entry point
la.pcrel t0, fw_arg2 la.pcrel t0, fw_arg2
st.d a2, t0, 0 st.d a2, t0, 0
#ifdef CONFIG_PAGE_SIZE_4KB
li.d t0, 0
li.d t1, CSR_STFILL
csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1
#endif
/* KSave3 used for percpu base, initialized as 0 */ /* KSave3 used for percpu base, initialized as 0 */
csrwr zero, PERCPU_BASE_KS csrwr zero, PERCPU_BASE_KS
/* GPR21 used for percpu base (runtime), initialized as 0 */ /* GPR21 used for percpu base (runtime), initialized as 0 */
@ -127,6 +132,11 @@ SYM_CODE_START(smpboot_entry)
JUMP_VIRT_ADDR t0, t1 JUMP_VIRT_ADDR t0, t1
#ifdef CONFIG_PAGE_SIZE_4KB
li.d t0, 0
li.d t1, CSR_STFILL
csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1
#endif
/* Enable PG */ /* Enable PG */
li.w t0, 0xb0 # PLV=0, IE=0, PG=1 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
csrwr t0, LOONGARCH_CSR_CRMD csrwr t0, LOONGARCH_CSR_CRMD