- Fix a race condition when clearing error count bits and toggling
the error interrupt throug the same register, in synopsys_edac -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmZAdYEACgkQEsHwGGHe VUrtORAAvwK9Ump8tGigXQ58aXY7a2b+iYrYiZtZkP23y0p81HJdYruanHeeLM4n CYKnuI+yKFP/e5jfxQj6vPj5sKk6U285+C2L/7MsHcfKf/bFzgjopzHLKYS+u6E6 YtjJQOFbozMvsDnF0BcxQf3OAiLsEkvA4JKb8gE7YqslMlJF5nhTVRRYtX3H+RBH FBupB/wZqvFS41igzTexkY89L71TlhRbP2hjUKScV4N5v9Jhh0m2PmApARW2EGkW X4RhqIs8kHVBseuNpanV/vBLJDFekJtZD95WLFltK10pGC306gMzEGVIj3H4Dnw3 qrgDK2hHxz9/i3ukHox5YoMKWVXBYTTo74a1kMvAoQxmCBERPQopUKu34nq9/NpQ ecWN6pFFwhwQAjdZkAoZgJknJtIaO8Ti4Uj9roN1PFgBDCConGXhJbFrU+z3WPfR aUk3VK4zBDyUSBkj9TJviWPm+8Se5HdcqgrFFqiLH5BYZIUWPYit8Q56LYzx5sKp +OgaguxjVwdyaPovFs6h/ae7/mJzzXn7FPRfOmeOH3KVFbo1X+Cu+o/lolXHfbvN KFfov33DMDuHLs6ECYrEM8OwIXXFcYBe/Pd7TePkaoEr9+7arujaBEJvMAyTQaWN x1OsOBo4Nxg7YYvfMVO7pKIv5Mn1LomAlOs8VZynRWAFeSqcaFk= =mBtC -----END PGP SIGNATURE----- Merge tag 'edac_urgent_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras Pull EDAC fix from Borislav Petkov: - Fix a race condition when clearing error count bits and toggling the error interrupt throug the same register, in synopsys_edac * tag 'edac_urgent_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: EDAC/synopsys: Fix ECC status and IRQ control race condition
This commit is contained in:
commit
ba16c1cf11
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@ -9,6 +9,7 @@
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#include <linux/edac.h>
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#include <linux/edac.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of.h>
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@ -299,6 +300,7 @@ struct synps_ecc_status {
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/**
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/**
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* struct synps_edac_priv - DDR memory controller private instance data.
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* struct synps_edac_priv - DDR memory controller private instance data.
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* @baseaddr: Base address of the DDR controller.
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* @baseaddr: Base address of the DDR controller.
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* @reglock: Concurrent CSRs access lock.
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* @message: Buffer for framing the event specific info.
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* @message: Buffer for framing the event specific info.
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* @stat: ECC status information.
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* @stat: ECC status information.
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* @p_data: Platform data.
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* @p_data: Platform data.
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@ -313,6 +315,7 @@ struct synps_ecc_status {
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*/
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*/
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struct synps_edac_priv {
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struct synps_edac_priv {
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void __iomem *baseaddr;
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void __iomem *baseaddr;
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spinlock_t reglock;
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char message[SYNPS_EDAC_MSG_SIZE];
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char message[SYNPS_EDAC_MSG_SIZE];
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struct synps_ecc_status stat;
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struct synps_ecc_status stat;
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const struct synps_platform_data *p_data;
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const struct synps_platform_data *p_data;
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@ -408,7 +411,8 @@ out:
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static int zynqmp_get_error_info(struct synps_edac_priv *priv)
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static int zynqmp_get_error_info(struct synps_edac_priv *priv)
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{
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{
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struct synps_ecc_status *p;
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struct synps_ecc_status *p;
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u32 regval, clearval = 0;
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u32 regval, clearval;
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unsigned long flags;
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void __iomem *base;
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void __iomem *base;
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base = priv->baseaddr;
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base = priv->baseaddr;
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@ -452,10 +456,14 @@ ue_err:
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p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
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p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
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p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
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p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
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out:
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out:
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clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
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spin_lock_irqsave(&priv->reglock, flags);
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clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
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clearval = readl(base + ECC_CLR_OFST) |
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ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT |
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ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
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writel(clearval, base + ECC_CLR_OFST);
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writel(clearval, base + ECC_CLR_OFST);
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writel(0x0, base + ECC_CLR_OFST);
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spin_unlock_irqrestore(&priv->reglock, flags);
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return 0;
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return 0;
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}
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}
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@ -515,24 +523,41 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
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static void enable_intr(struct synps_edac_priv *priv)
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static void enable_intr(struct synps_edac_priv *priv)
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{
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{
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unsigned long flags;
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/* Enable UE/CE Interrupts */
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/* Enable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
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writel(DDR_UE_MASK | DDR_CE_MASK,
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priv->baseaddr + ECC_CLR_OFST);
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else
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
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priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
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return;
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}
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spin_lock_irqsave(&priv->reglock, flags);
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writel(DDR_UE_MASK | DDR_CE_MASK,
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priv->baseaddr + ECC_CLR_OFST);
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spin_unlock_irqrestore(&priv->reglock, flags);
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}
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}
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static void disable_intr(struct synps_edac_priv *priv)
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static void disable_intr(struct synps_edac_priv *priv)
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{
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{
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unsigned long flags;
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/* Disable UE/CE Interrupts */
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/* Disable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
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writel(0x0, priv->baseaddr + ECC_CLR_OFST);
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else
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
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priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
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return;
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}
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spin_lock_irqsave(&priv->reglock, flags);
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writel(0, priv->baseaddr + ECC_CLR_OFST);
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spin_unlock_irqrestore(&priv->reglock, flags);
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}
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}
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/**
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/**
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@ -576,8 +601,6 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
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/* v3.0 of the controller does not have this register */
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/* v3.0 of the controller does not have this register */
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
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writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
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writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
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else
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enable_intr(priv);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -1357,6 +1380,7 @@ static int mc_probe(struct platform_device *pdev)
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priv = mci->pvt_info;
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priv = mci->pvt_info;
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priv->baseaddr = baseaddr;
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priv->baseaddr = baseaddr;
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priv->p_data = p_data;
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priv->p_data = p_data;
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spin_lock_init(&priv->reglock);
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mc_init(mci, pdev);
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mc_init(mci, pdev);
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