Short summary of fixes pull:
core: - fix connector debugging output meson: - dw-hdmi: power-up fixes - dw-hdmi: add badngap setting for g12 -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEchf7rIzpz2NEoWjlaA3BHVMLeiMFAmY9ynIACgkQaA3BHVML eiO/Pwf+Ie7fdPnJP/7aodAHRi/gQdwuxxjhLwRwENFP7bjjMhWV/jDnlI/senHx ISppKgEqhMmX3rrNn6tOGlZaWgFUi838fS4Nczfx0P1hvNjA2owlEqTIPoFsMHsP I1p0yJe4s0LpNp8weBc/IwuZSz0UkuDOsL6xQMUMh7OITdBk+iH9cRMD/+Sg9JgV NIzluRCDQ+x3vKmpcUzI9/cDbtVG8XAzPYRvugbHZsX5PwcgZxbsqQXN++uXzvZJ X2sSjlzqzzddFmUL18N+uaHf8MNd6BmcLxean4pxnEM+T90VyQdT52OgY2nzXhRK aN9Pz8WhRSlXaZEDKxm3VFVdaGuOIQ== =6ngs -----END PGP SIGNATURE----- Merge tag 'drm-misc-fixes-2024-05-10' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Short summary of fixes pull: core: - fix connector debugging output meson: - dw-hdmi: power-up fixes - dw-hdmi: add badngap setting for g12 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20240510072027.GA9131@linux.fritz.box
This commit is contained in:
commit
b61821bb32
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@ -2940,7 +2940,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
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dev->mode_config.max_width,
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dev->mode_config.max_height);
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else
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drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe",
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drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe\n",
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connector->base.id, connector->name);
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}
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@ -106,6 +106,8 @@
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
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#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
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#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
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#define PHY_CNTL1_INIT 0x03900000
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#define PHY_INVERT BIT(17)
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#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
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#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
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#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
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@ -130,6 +132,8 @@ struct meson_dw_hdmi_data {
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unsigned int addr);
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void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data);
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u32 cntl0_init;
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u32 cntl1_init;
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};
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struct meson_dw_hdmi {
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@ -384,26 +388,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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dw_hdmi_bus_fmt_is_420(hdmi))
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mode_is_420 = true;
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/* Enable clocks */
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regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
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/* Bring HDMITX MEM output of power down */
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regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
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/* Bring out of reset */
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
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/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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0x3, 0x3);
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/* Enable cec_clk and hdcp22_tmdsclk_en */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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0x3 << 4, 0x3 << 4);
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/* Enable normal output to PHY */
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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/* TMDS pattern setup */
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if (mode->clock > 340000 && !mode_is_420) {
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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@ -425,20 +409,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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/* Setup PHY parameters */
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meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);
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/* Setup PHY */
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
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0xffff << 16, 0x0390 << 16);
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/* BIT_INVERT */
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if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
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BIT(17), 0);
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else
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
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BIT(17), BIT(17));
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/* Disable clock, fifo, fifo_wr */
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
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@ -492,7 +462,9 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
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DRM_DEBUG_DRIVER("\n");
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
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/* Fallback to init mode */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
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}
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static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
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@ -610,11 +582,22 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = {
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.fast_io = true,
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};
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static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
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static const struct meson_dw_hdmi_data meson_dw_hdmi_gxbb_data = {
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.top_read = dw_hdmi_top_read,
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.top_write = dw_hdmi_top_write,
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.dwc_read = dw_hdmi_dwc_read,
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.dwc_write = dw_hdmi_dwc_write,
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.cntl0_init = 0x0,
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.cntl1_init = PHY_CNTL1_INIT | PHY_INVERT,
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};
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static const struct meson_dw_hdmi_data meson_dw_hdmi_gxl_data = {
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.top_read = dw_hdmi_top_read,
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.top_write = dw_hdmi_top_write,
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.dwc_read = dw_hdmi_dwc_read,
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.dwc_write = dw_hdmi_dwc_write,
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.cntl0_init = 0x0,
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.cntl1_init = PHY_CNTL1_INIT,
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};
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static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
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@ -622,6 +605,8 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
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.top_write = dw_hdmi_g12a_top_write,
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.dwc_read = dw_hdmi_g12a_dwc_read,
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.dwc_write = dw_hdmi_g12a_dwc_write,
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.cntl0_init = 0x000b4242, /* Bandgap */
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.cntl1_init = PHY_CNTL1_INIT,
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};
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static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
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meson_dw_hdmi->data->top_write(meson_dw_hdmi,
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HDMITX_TOP_CLK_CNTL, 0xff);
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/* Enable normal output to PHY */
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meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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/* Setup PHY */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
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/* Enable HDMI-TX Interrupt */
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meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
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HDMITX_TOP_INTR_CORE);
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@ -865,11 +857,11 @@ static const struct dev_pm_ops meson_dw_hdmi_pm_ops = {
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static const struct of_device_id meson_dw_hdmi_of_table[] = {
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{ .compatible = "amlogic,meson-gxbb-dw-hdmi",
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.data = &meson_dw_hdmi_gx_data },
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.data = &meson_dw_hdmi_gxbb_data },
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{ .compatible = "amlogic,meson-gxl-dw-hdmi",
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.data = &meson_dw_hdmi_gx_data },
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.data = &meson_dw_hdmi_gxl_data },
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{ .compatible = "amlogic,meson-gxm-dw-hdmi",
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.data = &meson_dw_hdmi_gx_data },
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.data = &meson_dw_hdmi_gxl_data },
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{ .compatible = "amlogic,meson-g12a-dw-hdmi",
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.data = &meson_dw_hdmi_g12a_data },
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{ }
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