- Automate CCS Mode setting during engine resets (Andi)
- Fix audio time stamp programming for DP (Chaitanya) - Fix parsing backlight BDB data (Karthikeyan) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmY70cgACgkQ+mJfZA7r E8pThQf8DddZyTSPC4vfN5QdBU8YvUDOOPx3osIURH+kDU7kdvQDHN1pfR4q3+Q2 afoViGlrpP2TqW7KW0WL6GDuDGnTMvvSryt4axvjaYqJJzSV9YjB2nZb1nWehcgj V8YFK+uRXbwFn1LoNmhvlaVguv85h25WqKbzNWHcvwB2N4hFIe+Goo/d9iME3p0Z r96KOo3O9z5P4NzGi/qBRWA8K9xfi69ePQKVSa9i2NbHPb074SAP7yjCa3V8oPcy QjLiOm7u+h/ilUAiVPUSdp0uHvA/Rrj8H07gdAFKpogteIzC75Fmhw+bLNaqJ+Kd BW0la/l+xc1pwKEji1vvhqxeJjMb6Q== =k/RY -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2024-05-08' of https://anongit.freedesktop.org/git/drm/drm-intel into drm-fixes - Automate CCS Mode setting during engine resets (Andi) - Fix audio time stamp programming for DP (Chaitanya) - Fix parsing backlight BDB data (Karthikeyan) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZjvTVEmQeVKVB2jx@intel.com
This commit is contained in:
commit
b356ead840
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@ -76,19 +76,6 @@ struct intel_audio_funcs {
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struct intel_crtc_state *crtc_state);
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};
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/* DP N/M table */
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#define LC_810M 810000
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#define LC_540M 540000
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#define LC_270M 270000
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#define LC_162M 162000
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struct dp_aud_n_m {
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int sample_rate;
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int clock;
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u16 m;
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u16 n;
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};
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struct hdmi_aud_ncts {
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int sample_rate;
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int clock;
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@ -96,60 +83,6 @@ struct hdmi_aud_ncts {
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int cts;
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};
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/* Values according to DP 1.4 Table 2-104 */
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static const struct dp_aud_n_m dp_aud_n_m[] = {
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{ 32000, LC_162M, 1024, 10125 },
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{ 44100, LC_162M, 784, 5625 },
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{ 48000, LC_162M, 512, 3375 },
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{ 64000, LC_162M, 2048, 10125 },
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{ 88200, LC_162M, 1568, 5625 },
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{ 96000, LC_162M, 1024, 3375 },
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{ 128000, LC_162M, 4096, 10125 },
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{ 176400, LC_162M, 3136, 5625 },
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{ 192000, LC_162M, 2048, 3375 },
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{ 32000, LC_270M, 1024, 16875 },
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{ 44100, LC_270M, 784, 9375 },
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{ 48000, LC_270M, 512, 5625 },
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{ 64000, LC_270M, 2048, 16875 },
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{ 88200, LC_270M, 1568, 9375 },
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{ 96000, LC_270M, 1024, 5625 },
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{ 128000, LC_270M, 4096, 16875 },
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{ 176400, LC_270M, 3136, 9375 },
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{ 192000, LC_270M, 2048, 5625 },
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{ 32000, LC_540M, 1024, 33750 },
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{ 44100, LC_540M, 784, 18750 },
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{ 48000, LC_540M, 512, 11250 },
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{ 64000, LC_540M, 2048, 33750 },
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{ 88200, LC_540M, 1568, 18750 },
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{ 96000, LC_540M, 1024, 11250 },
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{ 128000, LC_540M, 4096, 33750 },
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{ 176400, LC_540M, 3136, 18750 },
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{ 192000, LC_540M, 2048, 11250 },
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{ 32000, LC_810M, 1024, 50625 },
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{ 44100, LC_810M, 784, 28125 },
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{ 48000, LC_810M, 512, 16875 },
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{ 64000, LC_810M, 2048, 50625 },
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{ 88200, LC_810M, 1568, 28125 },
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{ 96000, LC_810M, 1024, 16875 },
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{ 128000, LC_810M, 4096, 50625 },
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{ 176400, LC_810M, 3136, 28125 },
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{ 192000, LC_810M, 2048, 16875 },
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};
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static const struct dp_aud_n_m *
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audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
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if (rate == dp_aud_n_m[i].sample_rate &&
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crtc_state->port_clock == dp_aud_n_m[i].clock)
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return &dp_aud_n_m[i];
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}
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return NULL;
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}
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static const struct {
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int clock;
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u32 config;
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@ -387,47 +320,17 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct i915_audio_component *acomp = i915->display.audio.component;
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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enum port port = encoder->port;
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const struct dp_aud_n_m *nm;
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int rate;
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u32 tmp;
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rate = acomp ? acomp->aud_sample_rate[port] : 0;
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nm = audio_config_dp_get_n_m(crtc_state, rate);
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if (nm)
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drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m,
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nm->n);
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else
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drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n");
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/* Enable time stamps. Let HW calculate Maud/Naud values */
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intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
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AUD_CONFIG_N_VALUE_INDEX |
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AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
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AUD_CONFIG_UPPER_N_MASK |
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AUD_CONFIG_LOWER_N_MASK |
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AUD_CONFIG_N_PROG_ENABLE,
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AUD_CONFIG_N_VALUE_INDEX);
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tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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if (nm) {
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tmp &= ~AUD_CONFIG_N_MASK;
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tmp |= AUD_CONFIG_N(nm->n);
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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}
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intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
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tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
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tmp &= ~AUD_CONFIG_M_MASK;
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tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
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tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
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if (nm) {
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tmp |= nm->m;
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tmp |= AUD_M_CTS_M_VALUE_INDEX;
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tmp |= AUD_M_CTS_M_PROG_ENABLE;
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}
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intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
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}
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static void
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@ -1042,22 +1042,11 @@ parse_lfp_backlight(struct drm_i915_private *i915,
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panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
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panel->vbt.backlight.controller = 0;
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if (i915->display.vbt.version >= 191) {
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size_t exp_size;
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const struct lfp_backlight_control_method *method;
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if (i915->display.vbt.version >= 236)
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exp_size = sizeof(struct bdb_lfp_backlight_data);
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else if (i915->display.vbt.version >= 234)
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exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
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else
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exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
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if (get_blocksize(backlight_data) >= exp_size) {
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const struct lfp_backlight_control_method *method;
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method = &backlight_data->backlight_control[panel_type];
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panel->vbt.backlight.type = method->type;
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panel->vbt.backlight.controller = method->controller;
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}
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method = &backlight_data->backlight_control[panel_type];
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panel->vbt.backlight.type = method->type;
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panel->vbt.backlight.controller = method->controller;
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}
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panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
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@ -897,11 +897,6 @@ struct lfp_brightness_level {
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u16 reserved;
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} __packed;
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#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \
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offsetof(struct bdb_lfp_backlight_data, brightness_level)
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#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \
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offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits)
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struct bdb_lfp_backlight_data {
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u8 entry_size;
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struct lfp_backlight_data_entry data[16];
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@ -8,14 +8,14 @@
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#include "intel_gt_ccs_mode.h"
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#include "intel_gt_regs.h"
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void intel_gt_apply_ccs_mode(struct intel_gt *gt)
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unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
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{
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int cslice;
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u32 mode = 0;
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int first_ccs = __ffs(CCS_MASK(gt));
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if (!IS_DG2(gt->i915))
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return;
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return 0;
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/* Build the value for the fixed CCS load balancing */
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for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
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XEHP_CCS_MODE_CSLICE_MASK);
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}
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intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
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return mode;
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}
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@ -8,6 +8,6 @@
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struct intel_gt;
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void intel_gt_apply_ccs_mode(struct intel_gt *gt);
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unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);
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#endif /* __INTEL_GT_CCS_MODE_H__ */
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@ -2859,6 +2859,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
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static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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{
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struct intel_gt *gt = engine->gt;
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u32 mode;
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if (!IS_DG2(gt->i915))
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return;
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* After having disabled automatic load balancing we need to
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* assign all slices to a single CCS. We will call it CCS mode 1
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*/
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intel_gt_apply_ccs_mode(gt);
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mode = intel_gt_apply_ccs_mode(gt);
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wa_masked_en(wal, XEHP_CCS_MODE, mode);
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}
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/*
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