drm/amdgpu: fix visible VRAM handling during faults
When we removed the hacky start code check we actually didn't took into
account that *all* VRAM pages needs to be CPU accessible.
Clean up the code and unify the handling into a single helper which
checks if the whole resource is CPU accessible.
The only place where a partial check would make sense is during
eviction, but that is neglitible.
Signed-off-by: Christian König <christian.koenig@amd.com>
Fixes: aed01a6804
("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: stable@vger.kernel.org
This commit is contained in:
parent
6fef2d4c00
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@ -819,7 +819,7 @@ retry:
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p->bytes_moved += ctx.bytes_moved;
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if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
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amdgpu_bo_in_cpu_visible_vram(bo))
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amdgpu_res_cpu_visible(adev, bo->tbo.resource))
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p->bytes_moved_vis += ctx.bytes_moved;
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if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
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@ -617,8 +617,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
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return r;
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if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
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bo->tbo.resource->mem_type == TTM_PL_VRAM &&
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amdgpu_bo_in_cpu_visible_vram(bo))
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amdgpu_res_cpu_visible(adev, bo->tbo.resource))
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amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
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ctx.bytes_moved);
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else
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@ -1272,23 +1271,25 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
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void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
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struct amdgpu_mem_stats *stats)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct ttm_resource *res = bo->tbo.resource;
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uint64_t size = amdgpu_bo_size(bo);
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struct drm_gem_object *obj;
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unsigned int domain;
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bool shared;
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/* Abort if the BO doesn't currently have a backing store */
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if (!bo->tbo.resource)
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if (!res)
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return;
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obj = &bo->tbo.base;
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shared = drm_gem_object_is_shared_for_memory_stats(obj);
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domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
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domain = amdgpu_mem_type_to_domain(res->mem_type);
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switch (domain) {
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case AMDGPU_GEM_DOMAIN_VRAM:
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stats->vram += size;
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if (amdgpu_bo_in_cpu_visible_vram(bo))
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if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
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stats->visible_vram += size;
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if (shared)
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stats->vram_shared += size;
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@ -1389,10 +1390,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
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/* Remember that this BO was accessed by the CPU */
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abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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if (bo->resource->mem_type != TTM_PL_VRAM)
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return 0;
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if (amdgpu_bo_in_cpu_visible_vram(abo))
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if (amdgpu_res_cpu_visible(adev, bo->resource))
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return 0;
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/* Can't move a pinned BO to visible VRAM */
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@ -1415,7 +1413,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
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/* this should never happen */
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if (bo->resource->mem_type == TTM_PL_VRAM &&
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!amdgpu_bo_in_cpu_visible_vram(abo))
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!amdgpu_res_cpu_visible(adev, bo->resource))
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return VM_FAULT_SIGBUS;
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ttm_bo_move_to_lru_tail_unlocked(bo);
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@ -1579,6 +1577,7 @@ uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
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*/
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u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct dma_buf_attachment *attachment;
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struct dma_buf *dma_buf;
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const char *placement;
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@ -1587,10 +1586,11 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
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if (dma_resv_trylock(bo->tbo.base.resv)) {
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unsigned int domain;
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domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
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switch (domain) {
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case AMDGPU_GEM_DOMAIN_VRAM:
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if (amdgpu_bo_in_cpu_visible_vram(bo))
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if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
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placement = "VRAM VISIBLE";
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else
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placement = "VRAM";
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@ -250,28 +250,6 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
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return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
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}
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/**
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* amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
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*/
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static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct amdgpu_res_cursor cursor;
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if (!bo->tbo.resource || bo->tbo.resource->mem_type != TTM_PL_VRAM)
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return false;
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amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
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while (cursor.remaining) {
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if (cursor.start < adev->gmc.visible_vram_size)
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return true;
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amdgpu_res_next(&cursor, cursor.size);
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}
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return false;
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}
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/**
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* amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
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*/
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@ -133,7 +133,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
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} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
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!(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
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amdgpu_bo_in_cpu_visible_vram(abo)) {
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amdgpu_res_cpu_visible(adev, bo->resource)) {
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/* Try evicting to the CPU inaccessible part of VRAM
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* first, but only set GTT as busy placement, so this
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return r;
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}
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/**
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* amdgpu_res_cpu_visible - Check that resource can be accessed by CPU
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* @adev: amdgpu device
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* @res: the resource to check
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*
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* Returns: true if the full resource is CPU visible, false otherwise.
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*/
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bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
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struct ttm_resource *res)
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{
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struct amdgpu_res_cursor cursor;
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if (!res)
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return false;
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if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT ||
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res->mem_type == AMDGPU_PL_PREEMPT)
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return true;
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if (res->mem_type != TTM_PL_VRAM)
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return false;
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amdgpu_res_first(res, 0, res->size, &cursor);
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while (cursor.remaining) {
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if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
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return false;
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amdgpu_res_next(&cursor, cursor.size);
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}
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return true;
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}
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/*
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* amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
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* amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy
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*
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* Called by amdgpu_bo_move()
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*/
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static bool amdgpu_mem_visible(struct amdgpu_device *adev,
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struct ttm_resource *mem)
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static bool amdgpu_res_copyable(struct amdgpu_device *adev,
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struct ttm_resource *mem)
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{
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u64 mem_size = (u64)mem->size;
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struct amdgpu_res_cursor cursor;
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u64 end;
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if (mem->mem_type == TTM_PL_SYSTEM ||
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mem->mem_type == TTM_PL_TT)
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return true;
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if (mem->mem_type != TTM_PL_VRAM)
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if (!amdgpu_res_cpu_visible(adev, mem))
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return false;
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amdgpu_res_first(mem, 0, mem_size, &cursor);
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end = cursor.start + cursor.size;
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while (cursor.remaining) {
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amdgpu_res_next(&cursor, cursor.size);
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/* ttm_resource_ioremap only supports contiguous memory */
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if (mem->mem_type == TTM_PL_VRAM &&
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!(mem->placement & TTM_PL_FLAG_CONTIGUOUS))
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return false;
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if (!cursor.remaining)
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break;
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/* ttm_resource_ioremap only supports contiguous memory */
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if (end != cursor.start)
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return false;
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end = cursor.start + cursor.size;
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}
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return end <= adev->gmc.visible_vram_size;
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return true;
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}
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/*
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if (r) {
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/* Check that all memory is CPU accessible */
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if (!amdgpu_mem_visible(adev, old_mem) ||
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!amdgpu_mem_visible(adev, new_mem)) {
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if (!amdgpu_res_copyable(adev, old_mem) ||
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!amdgpu_res_copyable(adev, new_mem)) {
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pr_err("Move buffer fallback to memcpy unavailable\n");
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return r;
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}
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@ -139,6 +139,9 @@ int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
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int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
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uint64_t start);
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bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
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struct ttm_resource *res);
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int amdgpu_ttm_init(struct amdgpu_device *adev);
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void amdgpu_ttm_fini(struct amdgpu_device *adev);
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void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
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