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- Add a new PCI ID which belongs to a new AMD CPU family 0x1a 

- Ensure that that last level cache ID is set in all cases, in the AMD
   CPU topology parsing code, in order to prevent invalid scheduling
   domain CPU masks
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmZAcSIACgkQEsHwGGHe
 VUr2Ww//Y+tY5iNLOCWCdD+nYcpGupletEUulvMLfEH42AZBNIHRyGCskuLWJAsw
 xBceY5uiTIAhKoSGUlbwIC+SWAdZQjxoF73KJQ55DQSOf7ogPW0SrQrvgI6QyTwb
 kRUNK+SQwqAVJBerFqz7gq9OhA6z+eewCDZPtcinIzWVC1zCVE0G4yEjAofDRF0F
 SbvS60fhFJCkQ/qi8Cz84tsO/+gTnYl3qyYPMCYkNtna5TyGv12tbDlSWSsATFBf
 0WdlXjRmuC1xLkTm/CQeCWrVG0yfvcPzL6lYkTgx9tGI1UBuifn9LZFy82+j8V1+
 tvAM3t7KC5pKa6xEok2L0+PflFsenaBEGoRZ1Os9nQvzCmnvTvLtEVn6DYrYykR4
 HRrH/TLWTSPxWUNSj4d6HPd0meAIqFZtvFPp2/ublr+VNNk3kYVXGVYEHFgnbJhY
 EIAj1H3tDfCToMZ7FjS8wJpaiX5LAw75/onK4IUhoQZdHsqzIxvfjhzvjepctHV2
 co5RFyY+W1K52AwZt4MHPNI4PUvNBcK9cqihDUZ3P5bKh7qWomTq/yrLuQSbuAhq
 /ImZgVPfmM9HKWQOyfr/6MmVQuis8TxYWL8mbQApoHEKpJOjlK9OziFnndQVV+Jh
 mSEIh8tcvUt0jKA2DfgiH6glkeBQOx5iaISeaMHOXIWPC/aW9vs=
 =y9je
 -----END PGP SIGNATURE-----

Merge tag 'x86_urgent_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Borislav Petkov:

 - Add a new PCI ID which belongs to a new AMD CPU family 0x1a

 - Ensure that that last level cache ID is set in all cases, in the AMD
   CPU topology parsing code, in order to prevent invalid scheduling
   domain CPU masks

* tag 'x86_urgent_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/topology/amd: Ensure that LLC ID is initialized
  x86/amd_nb: Add new PCI IDs for AMD family 0x1a
This commit is contained in:
Linus Torvalds 2024-05-12 08:54:28 -07:00
parent cf87f46fd3 5754ace3c3
commit 775a0eca33
3 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/x86/kernel/amd_nb.c
View File

@ -95,6 +95,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_DF_F3) },
{} {}

16
arch/x86/kernel/cpu/topology_amd.c
View File

@ -119,7 +119,7 @@ static bool parse_8000_001e(struct topo_scan *tscan, bool has_0xb)
return true; return true;
} }
static bool parse_fam10h_node_id(struct topo_scan *tscan) static void parse_fam10h_node_id(struct topo_scan *tscan)
{ {
union { union {
struct { struct {
@ -131,20 +131,20 @@ static bool parse_fam10h_node_id(struct topo_scan *tscan)
} nid; } nid;
if (!boot_cpu_has(X86_FEATURE_NODEID_MSR)) if (!boot_cpu_has(X86_FEATURE_NODEID_MSR))
return false; return;
rdmsrl(MSR_FAM10H_NODE_ID, nid.msr); rdmsrl(MSR_FAM10H_NODE_ID, nid.msr);
store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id); store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id);
tscan->c->topo.llc_id = nid.node_id; tscan->c->topo.llc_id = nid.node_id;
return true;
} }
static void legacy_set_llc(struct topo_scan *tscan) static void legacy_set_llc(struct topo_scan *tscan)
{ {
unsigned int apicid = tscan->c->topo.initial_apicid; unsigned int apicid = tscan->c->topo.initial_apicid;
/* parse_8000_0008() set everything up except llc_id */ /* If none of the parsers set LLC ID then use the die ID for it. */
tscan->c->topo.llc_id = apicid >> tscan->dom_shifts[TOPO_CORE_DOMAIN]; if (tscan->c->topo.llc_id == BAD_APICID)
tscan->c->topo.llc_id = apicid >> tscan->dom_shifts[TOPO_CORE_DOMAIN];
} }
static void topoext_fixup(struct topo_scan *tscan) static void topoext_fixup(struct topo_scan *tscan)
@ -187,10 +187,7 @@ static void parse_topology_amd(struct topo_scan *tscan)
return; return;
/* Try the NODEID MSR */ /* Try the NODEID MSR */
if (parse_fam10h_node_id(tscan)) parse_fam10h_node_id(tscan);
return;
legacy_set_llc(tscan);
} }
void cpu_parse_topology_amd(struct topo_scan *tscan) void cpu_parse_topology_amd(struct topo_scan *tscan)
@ -198,6 +195,7 @@ void cpu_parse_topology_amd(struct topo_scan *tscan)
tscan->amd_nodes_per_pkg = 1; tscan->amd_nodes_per_pkg = 1;
topoext_fixup(tscan); topoext_fixup(tscan);
parse_topology_amd(tscan); parse_topology_amd(tscan);
legacy_set_llc(tscan);
if (tscan->amd_nodes_per_pkg > 1) if (tscan->amd_nodes_per_pkg > 1)
set_cpu_cap(tscan->c, X86_FEATURE_AMD_DCM); set_cpu_cap(tscan->c, X86_FEATURE_AMD_DCM);

1
include/linux/pci_ids.h
View File

@ -580,6 +580,7 @@
#define PCI_DEVICE_ID_AMD_19H_M78H_DF_F3 0x12fb #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F3 0x12fb
#define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3 0x12c3 #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3 0x12c3
#define PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3 0x16fb #define PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3 0x16fb
#define PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3 0x12bb
#define PCI_DEVICE_ID_AMD_MI200_DF_F3 0x14d3 #define PCI_DEVICE_ID_AMD_MI200_DF_F3 0x14d3
#define PCI_DEVICE_ID_AMD_MI300_DF_F3 0x152b #define PCI_DEVICE_ID_AMD_MI300_DF_F3 0x152b
#define PCI_DEVICE_ID_AMD_VANGOGH_USB 0x163a #define PCI_DEVICE_ID_AMD_VANGOGH_USB 0x163a