pinctrl: samsung: add exynosautov920 pinctrl
Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Jaewon Kim
Krzysztof Kozlowski
parent
884fdaa53b
commit
6cf96df773
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@ -726,6 +726,146 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
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.num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
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};
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/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
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EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),
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EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),
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};
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/* pin banks of exynosautov920 pin-controller 1 (AUD) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = {
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EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28),
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};
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/* pin banks of exynosautov920 pin-controller 2 (HSI0) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = {
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EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24),
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};
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/* pin banks of exynosautov920 pin-controller 3 (HSI1) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = {
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EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28),
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};
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/* pin banks of exynosautov920 pin-controller 4 (HSI2) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = {
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EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28),
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};
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/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = {
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EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24),
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};
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/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = {
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EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28),
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};
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/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */
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static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = {
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EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24),
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EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28),
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};
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static const struct samsung_retention_data exynosautov920_retention_data __initconst = {
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.regs = NULL,
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.nr_regs = 0,
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.value = 0,
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.refcnt = &exynos_shared_retention_refcnt,
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.init = exynos_retention_init,
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};
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static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynosautov920_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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.retention_data = &exynosautov920_retention_data,
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}, {
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/* pin-controller instance 1 AUD data */
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.pin_banks = exynosautov920_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1),
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}, {
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/* pin-controller instance 2 HSI0 data */
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.pin_banks = exynosautov920_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 3 HSI1 data */
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.pin_banks = exynosautov920_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 4 HSI2 data */
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.pin_banks = exynosautov920_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 5 HSI2UFS data */
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.pin_banks = exynosautov920_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 6 PERIC0 data */
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.pin_banks = exynosautov920_pin_banks6,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 7 PERIC1 data */
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.pin_banks = exynosautov920_pin_banks7,
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.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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},
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};
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const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = {
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.ctrl = exynosautov920_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
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};
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/*
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* Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
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* gpio/pin-mux/pinconfig controllers.
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@ -281,7 +281,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
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unsigned int svc, group, pin;
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int ret;
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svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
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if (bank->eint_con_offset)
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svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
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else
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svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
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group = EXYNOS_SVC_GROUP(svc);
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pin = svc & EXYNOS_SVC_NUM_MASK;
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@ -490,6 +493,22 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
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.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
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};
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static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = {
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.chip = {
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.name = "exynosautov920_wkup_irq_chip",
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.irq_unmask = exynos_irq_unmask,
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.irq_mask = exynos_irq_mask,
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.irq_ack = exynos_irq_ack,
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.irq_set_type = exynos_irq_set_type,
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.irq_set_wake = exynos_wkup_irq_set_wake,
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.irq_request_resources = exynos_irq_request_resources,
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.irq_release_resources = exynos_irq_release_resources,
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},
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.eint_wake_mask_value = &eint_wake_mask_value,
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.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
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.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
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};
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/* list of external wakeup controllers supported */
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static const struct of_device_id exynos_wkup_irq_ids[] = {
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{ .compatible = "samsung,s5pv210-wakeup-eint",
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@ -502,6 +521,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
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.data = &exynos7_wkup_irq_chip },
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{ .compatible = "samsung,exynosautov9-wakeup-eint",
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.data = &exynos7_wkup_irq_chip },
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{ .compatible = "samsung,exynosautov920-wakeup-eint",
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.data = &exynosautov920_wkup_irq_chip },
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{ }
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};
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@ -31,6 +31,7 @@
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#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
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#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
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#define EXYNOS_SVC_OFFSET 0xB08
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#define EXYNOSAUTO_SVC_OFFSET 0xF008
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/* helpers to access interrupt service register */
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#define EXYNOS_SVC_GROUP_SHIFT 3
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@ -140,6 +141,30 @@
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.name = id \
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}
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#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
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{ \
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.type = &exynos850_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_con_offset = con_offs, \
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.eint_mask_offset = mask_offs, \
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.eint_pend_offset = pend_offs, \
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.name = id \
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}
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#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_con_offset = con_offs, \
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.eint_mask_offset = mask_offs, \
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.eint_pend_offset = pend_offs, \
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.name = id \
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}
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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@ -1324,6 +1324,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos850_of_data },
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{ .compatible = "samsung,exynosautov9-pinctrl",
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.data = &exynosautov9_of_data },
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{ .compatible = "samsung,exynosautov920-pinctrl",
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.data = &exynosautov920_of_data },
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{ .compatible = "tesla,fsd-pinctrl",
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.data = &fsd_of_data },
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#endif
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@ -362,6 +362,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
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extern const struct samsung_pinctrl_of_match_data fsd_of_data;
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extern const struct samsung_pinctrl_of_match_data gs101_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
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