LoongArch: Add la_abs macro implementation
Use the "la_abs macro" instead of the "la.abs pseudo instruction" to prepare for the subsequent PIE kernel. When PIE is not enabled, la_abs is equivalent to la.abs. Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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@ -274,4 +274,8 @@
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nor \dst, \src, zero
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nor \dst, \src, zero
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.endm
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.endm
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.macro la_abs reg, sym
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la.abs \reg, \sym
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.endm
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#endif /* _ASM_ASMMACRO_H */
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#endif /* _ASM_ASMMACRO_H */
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@ -86,7 +86,7 @@
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* new value in sp.
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* new value in sp.
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*/
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*/
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.macro get_saved_sp docfi=0
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.macro get_saved_sp docfi=0
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la.abs t1, kernelsp
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la_abs t1, kernelsp
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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csrrd t0, PERCPU_BASE_KS
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csrrd t0, PERCPU_BASE_KS
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LONG_ADD t1, t1, t0
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LONG_ADD t1, t1, t0
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@ -34,7 +34,7 @@ SYM_FUNC_END(__arch_cpu_idle)
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SYM_FUNC_START(handle_vint)
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SYM_FUNC_START(handle_vint)
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BACKUP_T0T1
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BACKUP_T0T1
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SAVE_ALL
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SAVE_ALL
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la.abs t1, __arch_cpu_idle
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la_abs t1, __arch_cpu_idle
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LONG_L t0, sp, PT_ERA
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LONG_L t0, sp, PT_ERA
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/* 32 byte rollback region */
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/* 32 byte rollback region */
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ori t0, t0, 0x1f
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ori t0, t0, 0x1f
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@ -43,7 +43,7 @@ SYM_FUNC_START(handle_vint)
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LONG_S t0, sp, PT_ERA
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LONG_S t0, sp, PT_ERA
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1: move a0, sp
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1: move a0, sp
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move a1, sp
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move a1, sp
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la.abs t0, do_vint
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la_abs t0, do_vint
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jirl ra, t0, 0
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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RESTORE_ALL_AND_RET
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SYM_FUNC_END(handle_vint)
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SYM_FUNC_END(handle_vint)
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@ -72,7 +72,7 @@ SYM_FUNC_END(except_vec_cex)
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SAVE_ALL
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SAVE_ALL
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build_prep_\prep
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build_prep_\prep
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move a0, sp
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move a0, sp
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la.abs t0, do_\handler
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la_abs t0, do_\handler
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jirl ra, t0, 0
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jirl ra, t0, 0
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668:
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668:
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RESTORE_ALL_AND_RET
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RESTORE_ALL_AND_RET
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@ -93,6 +93,6 @@ SYM_FUNC_END(except_vec_cex)
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BUILD_HANDLER reserved reserved none /* others */
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BUILD_HANDLER reserved reserved none /* others */
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SYM_FUNC_START(handle_sys)
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SYM_FUNC_START(handle_sys)
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la.abs t0, handle_syscall
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la_abs t0, handle_syscall
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jr t0
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jr t0
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SYM_FUNC_END(handle_sys)
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SYM_FUNC_END(handle_sys)
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@ -39,7 +39,7 @@ SYM_FUNC_START(handle_tlb_protect)
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move a1, zero
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move a1, zero
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csrrd a2, LOONGARCH_CSR_BADV
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csrrd a2, LOONGARCH_CSR_BADV
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REG_S a2, sp, PT_BVADDR
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REG_S a2, sp, PT_BVADDR
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la.abs t0, do_page_fault
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la_abs t0, do_page_fault
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jirl ra, t0, 0
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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RESTORE_ALL_AND_RET
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SYM_FUNC_END(handle_tlb_protect)
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SYM_FUNC_END(handle_tlb_protect)
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@ -115,7 +115,7 @@ smp_pgtable_change_load:
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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vmalloc_load:
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vmalloc_load:
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la.abs t1, swapper_pg_dir
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la_abs t1, swapper_pg_dir
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b vmalloc_done_load
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b vmalloc_done_load
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#endif
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#endif
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@ -186,7 +186,7 @@ tlb_huge_update_load:
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nopage_tlb_load:
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nopage_tlb_load:
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dbar 0
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dbar 0
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csrrd ra, EXCEPTION_KS2
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csrrd ra, EXCEPTION_KS2
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la.abs t0, tlb_do_page_fault_0
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la_abs t0, tlb_do_page_fault_0
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jr t0
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jr t0
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SYM_FUNC_END(handle_tlb_load)
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SYM_FUNC_END(handle_tlb_load)
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@ -262,7 +262,7 @@ smp_pgtable_change_store:
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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vmalloc_store:
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vmalloc_store:
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la.abs t1, swapper_pg_dir
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la_abs t1, swapper_pg_dir
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b vmalloc_done_store
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b vmalloc_done_store
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#endif
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#endif
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@ -335,7 +335,7 @@ tlb_huge_update_store:
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nopage_tlb_store:
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nopage_tlb_store:
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dbar 0
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dbar 0
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csrrd ra, EXCEPTION_KS2
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csrrd ra, EXCEPTION_KS2
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la.abs t0, tlb_do_page_fault_1
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la_abs t0, tlb_do_page_fault_1
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jr t0
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jr t0
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SYM_FUNC_END(handle_tlb_store)
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SYM_FUNC_END(handle_tlb_store)
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@ -410,7 +410,7 @@ smp_pgtable_change_modify:
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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vmalloc_modify:
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vmalloc_modify:
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la.abs t1, swapper_pg_dir
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la_abs t1, swapper_pg_dir
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b vmalloc_done_modify
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b vmalloc_done_modify
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#endif
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#endif
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@ -482,7 +482,7 @@ tlb_huge_update_modify:
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nopage_tlb_modify:
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nopage_tlb_modify:
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dbar 0
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dbar 0
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csrrd ra, EXCEPTION_KS2
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csrrd ra, EXCEPTION_KS2
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la.abs t0, tlb_do_page_fault_1
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la_abs t0, tlb_do_page_fault_1
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jr t0
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jr t0
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SYM_FUNC_END(handle_tlb_modify)
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SYM_FUNC_END(handle_tlb_modify)
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